Senior PCIe Design Engineer

Arm Holdings

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $161,500–$218,500 / yr
Posted: 34 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k

This role $190k

$140k most similar roles pay here $246k

This role pays less than 52% of similar roles. Most pay $173,275–$219,000 — the shaded band above. At the midpoint, this role pays about $190k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Senior PCIe Design Engineer

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The Senior PCIe Design Engineer joins an innovative team focused on integrating PCIe, CXL, and other IP components into SoCs. This role involves collaborating with project teams to review architectures, developing build specifications, writing micro-architecture specifications, and developing RTL while fixing bugs and running design checks. The engineer will also partner with verification and performance analysis teams to debug issues and improve system performance, while working with the backend team on floor planning, constraints, and timing closure. Key technical requirements include expertise in Verilog HDL, digital hardware design, and experience with PCIe, CXL, UCIe, and Ethernet subsystems. Candidates should be proficient in Perl or Python scripting and possess knowledge of CDC, RDC, X-Propagation, and Linting. The role addresses complex compute subsystem challenges within the domain of SoC development and high-speed interconnects.

Skills

Verilog HDL RTL SoC ARM PCIe CXL UCIe Ethernet Python Perl CDC RDC Linting Synthesis Timing Analysis DFT Floor Planning Power Management

What you'll do

Integrate PCIe, CXL, and other IP components into SoC designs.
Write micro-architecture specifications and develop detailed build specifications.
Develop RTL code and perform bug fixes for integrated subsystems.
Run design checks including CDC, RDC, X-Propagation, and Linting.
Partner with performance teams to evaluate and improve system performance.
Assist the backend team with floor planning, writing constraints, and timing closure.
Develop and enhance internal design methodologies used by the engineering team.
Guide and support other team members to ensure successful project completion.

What we're looking for

Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field.
5+ years of experience in the design of complex compute subsystems or SoCs.
Strong knowledge of digital hardware design and Verilog HDL.
Experience developing and integrating subsystems for PCIe, CXL, UCIe, and Ethernet.
Experience creating design specifications and developing RTL for SoC projects and compute platforms.
Experience in static design checks including CDC, RDC, X-Propagation, and Linting.
Proficiency with Perl, Python, or other scripting languages.
Experience with ARM-based designs, ARM System Architectures, leading teams, synthesis, power management, or DFT (preferred).

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