Senior Serdes System Design Engineer Architect

Broadcom

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Austin, TXSan Jose, CAIrvine, CA
Salary
$143,800–$230,000 / yr
Posted
29 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 8, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k
This role $187k
$133k most similar roles pay here $240k

This role pays more than 58% of similar roles. Most pay $151,086–$213,531 — the shaded band above. At the midpoint, this role pays about $187k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · Senior Serdes System Design Engineer Architect

As a Senior Serdes System Design Engineer/Architect in the Physical Layer Products Division, you will join a team of expert communication system and mixed-signal ASIC designers. You will be responsible for designing, verifying, and implementing advanced signal processing algorithms for high-speed Serdes at speeds of 100G+. Your daily work involves developing channel models, defining block requirements, and creating bit-exact MATLAB and C/C++ system models to evaluate architectural tradeoffs. You will collaborate with analog and digital designers to implement features like PAM modulation, adaptive equalizers, and FEC in advanced silicon nodes while performing lab testing and firmware debugging. The role requires expert knowledge in communication theory, DSP algorithms, transmission line theory, and s-parameters. You will address technical challenges in wireline communications, including compensation for analog circuit non-idealities and supporting next-generation standards like IEEE and OIF.

What you'll do

  • Develop channel models and run simulations to define Serdes architecture.
  • Define and document signal processing block requirements, architecture, and lab test plans.
  • Create bit-exact MATLAB and C/C++ system models for simulation and verification.
  • Run system-level simulation suites to evaluate architectural tradeoffs.
  • Perform vector matching verification with RTL simulations in coordination with the design team.
  • Develop, test, and debug firmware associated with physical layer functionality.
  • Conduct lab testing and debugging of Serdes products.
  • Create documentation, application notes, and marketing collateral for customer support.

What we're looking for

  • B.S.E.E. with 12+ years of relevant experience or M.S.E.E. with 10 years of experience.
  • Expert knowledge in Communication Theory and Digital Signal Processing algorithms.
  • Working knowledge of Analog circuit behavior and Transmission line theory including s-parameters.
  • Expertise in MATLAB and C/C++ programming.
  • Good hands-on skills in the lab for testing and debugging.
  • Experience in designing high-speed Clock and Data Recovery (CDR) PLLs (preferred).
  • Experience in equalization techniques for wireline communication applications such as read-channel (preferred).
  • RTL coding, knowledge of IEEE 802.3/OIF standards, and PCIe Gen6/Gen7 standards (preferred).

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