Senior Serdes System Design Engineer/Architect

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TXSan Jose, CAIrvine, CA
Salary: $143,800–$230,000 / yr
Employment: Full-time
Posted: 75 days ago
Freshness: Confirmed live yesterday
Closes: Feb 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k

This role $187k

$132k $241k

below market most similar roles pay here above market

This role pays more than 61% of similar roles. Most pay $150,374–$212,493 — the blue band above. At the midpoint, this role pays about $187k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Senior Serdes System Design Engineer/Architect

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The Senior Serdes System Design Engineer/Architect joins the Physical Layer Products Division to design, verify, and implement advanced signal processing algorithms for high-speed Serdes products at speeds of 100G+. You will develop channel models, define architecture requirements, and create bit-exact MATLAB and C/C++ system models to evaluate architectural tradeoffs. Key responsibilities include implementing PAM modulation, adaptive equalizers, multi-dimensioned FEC, and digital filters while integrating with analog functions to compensate for circuit non-idealities. You will collaborate with analog and digital designers on advanced silicon technology nodes and perform lab testing and firmware debugging. Required expertise includes Communication Theory, Digital Signal Processing, Transmission line theory, and s-parameters. The role focuses on developing next-generation wireline communications standards for IEEE and OIF.

Skills

Digital Signal Processing MATLAB C/C++ SerDes RTL ASIC Communication Theory FEC CDR PCIe Gen6/Gen7 IEEE 802.3 OIF Signal Processing Algorithms Firmware Vector Matching Transmission Line Theory

What you'll do

Develop channel models and run simulations to define Serdes architecture.
Define and document signal processing block requirements, architecture, and lab test plans.
Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
Run system-level simulation suites to evaluate architectural tradeoffs.
Perform vector matching verification with RTL simulations.
Develop, test, and debug firmware associated with physical layer functionality.
Conduct lab testing and debugging of Serdes products.
Develop documentation, application notes, and provide customer support.

What we're looking for

B.S.E.E. plus 12+ years relevant experience or M.S.E.E. plus 10 years relevant experience.
Expert knowledge in Communication Theory.
Expert knowledge in Digital Signal Processing algorithms.
Working knowledge of Analog circuit behavior.
Working knowledge of Transmission line theory and s-parameter.
Expert in MATLAB and C/C++ programming.
Good hands-on skills in the lab.
Experience in designing high-speed Clock and Data Recovery (CDR) PLLs (preferred).
Experience in equalization techniques for wireline communication applications (preferred).
RTL coding (preferred).
Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes and PCIe Gen6/Gen7 standards (preferred).

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