Senior Serdes System Design Engineer Architect

What you'll do

• Develop channel models and run simulations to define Serdes architecture.
• Define and document signal processing block requirements, architecture, and lab test plans.
• Create bit-exact MATLAB and C/C++ system models for simulation and verification.
• Run system-level simulation suites to evaluate architectural tradeoffs.
• Perform vector matching verification with RTL simulations in coordination with the design team.
• Develop, test, and debug firmware associated with physical layer functionality.
• Conduct lab testing and debugging of Serdes products.
• Create documentation, application notes, and marketing collateral for customer support.

What we're looking for

• A B.S.E.E. degree with 8+ years of relevant experience or an M.S.E.E. with 6 years of experience is required.
• Expert knowledge in Communication Theory and Digital Signal Processing algorithms is required.
• Working knowledge of Analog circuit behavior and Transmission line theory including s-parameters is required.
• Proficiency in MATLAB and C/C++ programming is required.
• Hands-on skills in a laboratory environment are required.
• Experience designing high-speed Clock and Data Recovery (CDR) PLLs is preferred.
• Experience in equalization techniques for wireline communication applications like read-channel is preferred.
• RTL coding, and knowledge of IEEE 802.3/OIF or PCIe Gen6/Gen7 standards are preferred.