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UVM System Verilog Python PCIe CXL AMBA AXI CHI Simulations Generative AI Coverage Signoff +6 more Show less

UVM SystemVerilog Verilog Python Perl PCIe CXL Ethernet ASIC FPGA Object-Oriented Programming Scripting Simulation HLS Verification Automation High-Speed Connectivity +11 more Show less

PCIe UVM System Verilog Verilog NVMe RDMA SoC Digital Design Computer Architecture Verification IP Tapeout Data Link Layer +7 more Show less

CPU Verification Micro-architecture Assertion Gate-level Simulation Assembly Mixed signal Verification Coverage Collection Silicon bringup Waveform Viewers Simulators RIS Cache Coherence +7 more Show less

Physical Verification DRC LVS ERC Antenna Calibre Python TCL Perl Shell Ansible Linux Azure EntraID PDK CAD Flow Automation IC Design +12 more Show less

SystemVerilog UVM ASIC Verification NoC AMBA AXI CHI Python Perl TCL SVA Formal Verification Emulation Palladium Veloce SoC Architecture Fabric and Interconnect Verification +11 more Show less

SystemVerilog UVM ASIC Verification NoC AMBA AXI CHI Python Perl TCL SVA Formal Verification Emulation Palladium Veloce SoC Architecture Scripting +11 more Show less

System Verilog UVM Verilog VHDL C C++ Python Ruby Perl Makefiles Agile FPGA Emulation Firmware Hardware Design Silicon Verification Functional Coverage Assertion Scripting +14 more Show less

Questa VCS Jasper Gold Verdi Python Perl SoC DFT JTAG TAP UPF RTL Scripting Functional Verification +9 more Show less

Python Matlab C/C++ LabVIEW Spectrum Analyzers Network Analyzers Vector Signal Generators Oscilloscopes CAD Link Budget Analysis Signal Chain Characterization Test Automation CI/CD Source Control DFT DFM +11 more Show less

SystemVerilog UVM Verilog VHDL Python C++ C TCL Perl Linux VLSI Design Digital Design Formal Verification Assertion-Based Verification Verdi DVE Questa JasperGold Cadence Jasper Simulation Tools +15 more Show less

System Verilog UVM Verilog ASIC Verification PCIe CXL NVMe Ethernet Python Perl FPGA HLS Computer Architecture Scripting Automation Simulation Tools +11 more Show less

SystemVerilog UVM Verilog C Python Perl Tcl Formal Verification AXI AHB Cryptography Secure Boot Hardware/Firmware Co-verification SoC Clock Domain Crossing +10 more Show less

Python Ruby C ASIC Linux TCP/IP BGP OSPF LACP VXLAN Docker Kubernetes CI/CD Wireshark Spirent TestCenter Avalanche Ixia Breaking Point +13 more Show less

Questa VCS Jasper Gold Verdi UPF Python Perl SoC DFT JTAG TAP RTL Scripting Functional Verification Static Simulation Dynamic Simulation +11 more Show less

DRC LVS PERC ESD Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT tapeout Advanced Nodes Rule Deck Validation +14 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less