This role pays less than
65%
of similar roles. Most pay
$177,250–$222,250
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$200k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
518 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 505 roles with salary data.
The Senior IP Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization to support cloud infrastructure. This role involves owning or leading verification for complex flows at the subsystem, IP, or block level while collaborating with partner teams to define strategies and test plans. Day-to-day responsibilities include developing UVM-based verification environments, running and debugging simulations, and applying random-stimulus and coverage-based techniques to identify bugs. The candidate will also innovate on verification efficiency through new methodologies, tools, and generative AI solutions while mentoring others. Technical requirements include experience with SystemVerilog Test Bench, Python for post-processing, and protocols such as CHI, AMBA, and AXI. The role focuses on the pre-silicon verification of hardware components like fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and power management.
Lead verification of complex flows at the subsystem, IP, or block level.
Define verification strategies and test plans in collaboration with partner teams.
Develop UVM-based verification environments to run and debug simulations for quality assurance.
Apply random-stimulus and coverage-based techniques to identify bugs and meet test plan goals.
Innovate new methodologies and tools to improve overall verification efficiency.
Integrate generative AI solutions into daily verification workflows and tasks.
Coach and mentor team members through active knowledge sharing.
What we're looking for
Must have a Doctorate with 1+ years experience, a Master's with 4+ years experience, or a Bachelor's with 5+ years of technical engineering experience.
Ability to pass Microsoft Cloud Background Check and meet export control regulations regarding citizenship or residency status.
Experience developing UVM-based verification environments and using random-stimulus and coverage-based techniques.
Experience driving IP verification for full product cycles from definition to silicon, including test plans and coverage signoff (preferred).
Demonstrated experience in fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, power management, or protocol bridges (preferred).
Experience verifying designs using CHI, AMBA, and AXI protocols (preferred).
Experience creating or maintaining test benches using UVM, SystemVerilog, or Python (preferred).
Experience applying generative AI solutions to verification work or day-to-day tasks (preferred).