Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$160,000–$225,000 / yr
Posted
today

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Competitive pay

How this pay compares to similar roles

Similar $187k
This role $192k
$144k most similar roles pay here $234k

This role pays more than 56% of similar roles. Most pay $158,400–$216,250 — the shaded band above. At the midpoint, this role pays about $192k versus about $187k for comparable roles.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

As a Senior Full Chip Physical Verification Engineer in the Silicon Engineering team, you will own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using tools like Calibre, ICV, or Pegasus. Your daily tasks include developing and optimizing physical verification flows for advanced node SoCs, interpreting foundry Design Rule Manuals (DRM), debugging complex violations, coordinating tapeout readiness across design teams, and engaging with foundries to resolve ambiguities. You will leverage AI agents to automate rule deck validation and signoff reporting workflows. The role requires deep expertise in SOC top-level physical design flows, IP integration, DRC/LVS methodologies, scripting skills (csh/bash, Perl, Python), and experience at advanced nodes (4nm and below) with large SoC designs (>10M gates).

What you'll do

  • Own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
  • Develop and optimize physical verification flows for advanced node SoCs.
  • Interpret foundry Design Rule Manuals (DRM) to implement rule updates in verified flows.
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
  • Coordinate tapeout readiness by managing signoff processes with block, top-level, and Hard IP design teams.

What we're looking for

  • Deep expertise in DRC, LVS, PERC, and ESD verification methodologies.
  • Hands-on experience with Calibre, ICV (IC Validator), or Pegasus tools.
  • Extensive knowledge of SOC top-level physical design flows and IP integration.
  • Experience working on advanced node SoCs (>4nm) and large designs (>10M gates).
  • Excellent scripting skills in csh/bash, Perl, Python, TCL, Makefile.
  • Direct experience with foundry Design Rule Manuals (DRM) and waiver requests.

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