Senior Full Chip Physical Verification Engineer

What you'll do

• Execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
• Develop, maintain, and optimize physical verification flows for advanced node SoCs.
• Interpret foundry Design Rule Manuals and translate rule updates into verified flow changes.
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
• Perform ESD verification to validate protection strategies and CDM/HBM compliance.
• Coordinate signoff across block and top-level teams to drive tapeout readiness.
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Leverage AI agents to automate rule deck validation and violation triage workflows.

What we're looking for

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of ASIC and/or physical design flow development experience in industry.
• Ability to work extended hours and weekends as needed to meet critical project milestones.
• Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
• Experience and deep understanding of SOC top level physical design flows (preferred).
• Experience in IP integration such as memories, I/Os, analog IPs, SerDes, or DDR (preferred).
• Deep expertise in DRC, LVS, PERC, and ESD verification methodologies (preferred).
• Hands-on proficiency with Calibre, ICV, or Pegasus (preferred).