Principal Silicon Design Verification Engineer

What you'll do

• Perform functional validation of PCIe IP at Block, Cluster, or Fullchip levels.
• Utilize UVM test benches and Verification IP (VIP) for hardware verification.
• Develop comprehensive test plans and write unit tests for functional validation.
• Create and manage regression suites to ensure system stability.
• Debug failures and drive timely resolutions during the verification process.
• Innovate new methodologies and tools to improve overall validation efficiency.
• Ensure code coverage and functional coverage goals are met for successful tapeout.

What we're looking for

• A Bachelor's degree plus 8 years of experience, Master's plus 6 years, or Doctorate plus 3 years in a relevant engineering field is required.
• Ability to pass Microsoft Cloud Background Check and other government security screening requirements is required.
• Experience with protocol verification for PCIe (especially Gen6/Gen7) and related standards like NVMe or RDMA is preferred.
• Experience with Cluster, SoC, or Fullchip level verification is preferred.
• Prior verification experience with PCIe at both the Transaction and Data Link Layer is preferred.
• Strong proficiency in Verilog, SystemVerilog, and UVM based testbench environments is preferred.
• A good understanding of computer architecture and digital design fundamentals is preferred.
• Experience building UVM testbenches, managing regressions, and meeting coverage goals to successful tapeout is preferred.