Principal Design Verification Engineer

SpaceX

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
113 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $193k
$134k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $169,625–$216,250.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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TL;DR · Principal Design Verification Engineer

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As a Principal Design Verification Engineer (Silicon Engineering), you will join cross-disciplinary teams to develop next-generation ASICs for space and ground infrastructure. You will be responsible for digital ASIC and FPGA verification at both the block and system levels, leading and executing test plans from inception through completion. Your daily work involves pre-silicon verification, chip bring-up, and post-silicon validation to ensure complex digital designs are fully verified. The role requires expertise in UVM, OVM, or VMM methodologies, along with strong object-oriented programming, constrained random verification, and coverage model implementation. You will utilize scripting languages like Python for automation while navigating the technical challenges of expanding Starlink network capabilities. This position focuses on solving connectivity problems by developing high-performance hardware components designed to function reliably in orbital environments and global ground networks.

Skills

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models

What you'll do

  • Perform digital ASIC and FPGA verification at both block and system levels.
  • Lead and execute verification test plans from inception through completion.
  • Conduct pre-silicon verification for next-generation ASICs.
  • Execute chip bring-up and post-silicon validation processes.
  • Develop complex test benches to verify intricate digital designs.
  • Implement coverage models and analyze results to ensure design integrity.
  • Utilize scripting languages like Python to automate verification tasks.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience with design verification and test bench development.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee for ITAR compliance.
  • Experience with verification methodologies such as UVM, OVM, or VMM.
  • Strong object-oriented programming knowledge and coding skills.
  • Experience in constrained random verification and developing test plans.
  • Proficiency in scripting languages like Python for automation.
  • Experience with RTL design, chip bring-up, and post-silicon validation.

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