Principal Design Verification Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Austin, TXIrvine, CARedmond, WASunnyvale, CA
Posted
159 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $196k
$135k $240k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,500–$223,000.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal Design Verification Engineer

Role Posting Log in to save

The Principal Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on the Starlink satellite constellation, specifically building chips that enable global broadband connectivity. The engineer is responsible for digital ASIC and FPGA verification at both the block and system levels. Key duties include leading and executing verification test plans, managing milestones from beginning to end, and contributing to pre-silicon verification, chip bring-up, and post-silicon validation. Required skills include 10+ years of experience in design verification and test bench development. Preferred technical competencies include UVM/OVM/VMM methodologies, object-oriented programming, constrained random verification, and Python for automation. The role requires solving complex digital design problems to expand the performance and capabilities of the Starlink network.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design

What you'll do

  • Perform digital ASIC and FPGA verification at both the block and system levels.
  • Lead and execute verification test plans, development, and milestones from start to finish.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation processes.
  • Execute all necessary steps to fully verify complex digital designs independently.
  • Develop and implement coverage models to analyze verification results.
  • Use scripting languages like Python to automate verification tasks.
  • Apply UVM/OVM/VMM methodologies to ensure robust design verification.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience with design verification and test bench development.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM/OVM/VMM (preferred).
  • Strong object-oriented programming, problem-solving, and coding skills (preferred).
  • Experience in constrained random verification, scripting languages like Python, and post-silicon validation (preferred).
  • Ability to work extended hours and weekends as needed to meet critical milestones.

Related searches

More Principal Design Verification Engineer jobs Principal Design Verification Engineer jobs in Austin All jobs at SpaceX

More like this

Similar roles

Principal Design Verification Engineer

SpaceX

Redmond, WA +3 159 days ago $210,000–$335,000
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save

Principal Design Verification Engineer

SpaceX

Irvine, CA +3 159 days ago $210,000–$335,000
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save

Principal Design Verification Engineer

SpaceX

Palo Alto, CA +4 159 days ago $210,000–$355,000
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save

Design Verification Engineer

SpaceX

Austin, TX 105 days ago
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save

Design Verification Engineer

SpaceX

Redmond, WA 105 days ago $125,000–$145,000
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save

Design Verification Engineer

SpaceX

Irvine, CA 105 days ago $125,000–$145,000
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save