Principal Design Verification Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$210,000–$335,000 / yr
Posted
113 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $272k
$120k most similar roles pay here $358k

This role pays more than 95% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $272k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Principal Design Verification Engineer

The Principal Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on the Starlink network, specifically creating hardware that enables global connectivity in previously inaccessible areas. The engineer is responsible for digital ASIC and FPGA verification at both block and system levels, leading test plan execution from inception through completion. Key responsibilities include pre-silicon verification, chip bring-up, and post-silicon validation of complex digital designs. To succeed, the candidate must possess expertise in UVM, OVM, or VMM methodologies, along with strong object-oriented programming and coding skills. The role requires proficiency in constrained random verification, coverage model implementation, and scripting languages like Python for automation. This position addresses critical hardware challenges to expand the performance and capabilities of satellite communication systems.

What you'll do

  • Perform digital ASIC and FPGA verification at both block and system levels.
  • Lead and execute verification test plans from inception through completion.
  • Conduct pre-silicon verification for next-generation ASICs.
  • Execute chip bring-up and post-silicon validation processes.
  • Develop and implement coverage models to analyze verification results.
  • Create automated scripts using languages like Python to streamline verification workflows.
  • Verify complex digital designs independently as a hands-on technical lead.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience with design verification and test bench development.
  • Must be a U.S. citizen, permanent resident, refugee, or asylee to meet ITAR requirements.
  • Experience with verification methodologies such as UVM, OVM, or VMM.
  • Strong object-oriented programming knowledge and coding skills.
  • Experience in constrained random verification and developing test plans.
  • Proficiency in scripting languages like Python for automation.
  • Experience with RTL design, chip bring-up, and post-silicon validation.

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