Principal Design Verification Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Redmond, WAAustin, TXIrvine, CASunnyvale, CA
Salary
$210,000–$335,000 / yr
Posted
159 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $272k
$123k $358k
below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $272k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Principal Design Verification Engineer

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The Principal Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on the Starlink satellite constellation, solving the technical challenge of providing reliable broadband internet to remote areas. The engineer is responsible for digital ASIC and FPGA verification at both the block and system levels. Key duties include leading verification test plans, executing milestones from beginning to end, and contributing to pre-silicon verification, chip bring-up, and post-silicon validation. Required expertise includes UVM, OVM, or VMM methodologies, object-oriented programming, and constrained random verification. Candidates must demonstrate proficiency in Python for automation, RTL design, and coverage model implementation to ensure the performance and capabilities of the global satellite network.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models

What you'll do

  • Perform digital ASIC and FPGA verification at both the block and system levels.
  • Lead and execute verification test plans, development, and milestones from start to finish.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Execute all necessary steps to fully verify complex digital designs.
  • Develop and implement coverage models to analyze verification results.
  • Use scripting languages like Python to automate verification processes.
  • Apply UVM/OVM/VMM methodologies to ensure robust design verification.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience with design verification and test bench development.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM/OVM/VMM (preferred).
  • Strong object-oriented programming, problem-solving, and coding skills (preferred).
  • Experience with constrained random verification, scripting languages like Python, and post-silicon validation (preferred).

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