Lead IP Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Closes: Sep 24, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $250k

$132k most similar roles pay here $318k

This role pays more than 86% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $250k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

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At a glance

TL;DR · Lead IP Verification Engineer

Role Posting Log in to save

As a Lead IP Verification Engineer in the AECG Group, you will join the front-end design verification team to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions. You will collaborate with architecture, hardware design, firmware, and product engineering teams to architect and implement IP or subsystem-level UVM verification environments including monitors, scoreboards, and reusable components. Your daily work involves developing comprehensive verification plans, creating directed and constrained-random tests, executing regressions, and debugging failures to ensure high functional coverage for FPGA and ASIC solutions. You will utilize SystemVerilog, Verilog, Python, and Perl while leveraging UVM methodologies to verify high-speed protocols like PCIe Gen6 and 400G Ethernet. The role focuses on solving complex technical challenges in high-speed connectivity features and improving development efficiency through automation and AI-assisted tools.

Skills

UVM SystemVerilog Verilog Python Perl PCIe CXL Ethernet ASIC FPGA Object-Oriented Programming Scripting Simulation HLS Verification Automation High-Speed Connectivity

What you'll do

Architect and implement IP or subsystem-level UVM verification environments including monitors, scoreboards, and checkers.
Define and verify new PCIe, CXL, and high-speed connectivity features in collaboration with cross-functional teams.
Develop comprehensive verification plans covering feature interactions, hardware/software integration, and performance requirements.
Create directed and constrained-random tests to ensure high functional coverage and design quality.
Execute regressions and debug failures to achieve first-pass silicon success for next-generation IP solutions.
Drive verification automation, methodology improvements, and the adoption of AI-assisted tools to increase productivity.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience with ASIC/IP verification using UVM methodology (preferred).
Expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments (preferred).
Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet (preferred).
Proficiency in scripting and automation using Python, Perl, or similar languages (preferred).
Experience working across the ASIC/FPGA development lifecycle from planning through tape-out (preferred).
Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements (preferred).
Technical leadership, mentoring experience, and knowledge of computer architecture or AI-driven verification methodologies (preferred).

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