Security IP Verification Engineer

Arm Holdings

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$161,500–$218,500 / yr
Posted
55 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $190k
$134k most similar roles pay here $235k

This role pays more than 55% of similar roles. Most pay $162,000–$222,250 — the shaded band above. At the midpoint, this role pays about $190k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Security IP Verification Engineer

The Security IP Verification Engineer joins the Arm Security IP Team to define and realize Hardware Security IP and subsystems for pioneering SoC designs. This role involves developing test plans, testbenches, verification models, and strategies while partnering with design teams for functional sign-off, power optimization, and performance improvements. The engineer will build and maintain testbenches using SystemVerilog, UVM, Verilog, and C, while also contributing to shared design and verification methodologies across the organization. Key technical requirements include expertise in digital hardware Verilog HDL, Formal verification, and scripting languages like Perl, Python, or Tcl. Candidates must possess experience in complex architectures involving AXI/AHB protocols, multi-clock domains, and firmware/hardware co-verification. The work focuses on critical security domains including Cryptography, Key Management, Hardware Root of Trust, Secure Boot, and embedded microprocessor systems.

What you'll do

  • Develop test plans, testbenches, verification models, and test strategies for Hardware Security IP and subsystems.
  • Create UVM, SystemVerilog/Verilog, and C testbenches to verify security features like cryptography and secure boot.
  • Debug test failures and technical issues within the design and verification flow.
  • Partner with the design team to achieve functional sign-off and optimize power and performance.
  • Contribute to the development and enhancement of shared design and verification methodologies across Arm.
  • Mentor team members to ensure the successful completion of projects.
  • Coordinate with Project Management on initiatives, project plans, and schedules.

What we're looking for

  • Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a similar field.
  • Over 5 years of experience in design or verification of sophisticated IP, embedded compute subsystems, or SoCs.
  • Solid understanding of Verilog HDL and verification strategies including SystemVerilog UVM, C, Formal, and Hardware/Firmware co-verification.
  • Experience in Security Hardware, Embedded Processor Systems, Applied Cryptography, Secure Boot, and Key Management.
  • Proven experience in complex digital IP architecture including multi-clock domains, AXI/AHB protocols, multi-power domains, and reset architectures.
  • Experience with scripting languages such as Perl, Python, or Tcl.
  • Low-level programming experience in C and Assembler, including firmware debug and tarmac logging.
  • Experience with ARM-based designs or ARM System Architectures (preferred); experience with formal verification or clock domain crossing (preferred).

More like this

Similar roles

Security IP Design Engineer

Arm Holdings

Austin, TX +2 55 days ago $161,500–$218,500
Verilog SystemVerilog UVM OVM SoC Design Applied Cryptography Secure Boot Key Management AXI AHB Python TCL Perl UPF CDC RDC LINT Timing Analysis Synthesis

Senior IP Verification Engineer

Arm Holdings

Chandler, AZ 69 days ago $161,500–$218,500
Questa VCS Jasper Gold Verdi UPF Python Perl SoC DFT JTAG TAP RTL Scripting Functional Verification Static Simulation Dynamic Simulation
Hybrid

Principal IP Verification Engineer

Arm Holdings

Chandler, AZ 28 days ago $249,900–$338,100
Questa VCS Jasper Gold Verdi Python Perl SoC DFT JTAG TAP UPF RTL Scripting Functional Verification

Custom SOC IP Verification Engineer

Nvidia

Santa Clara, CA +1 17 days ago $168,000–$264,500
SystemVerilog UVM ASIC Verification NoC AMBA AXI CHI Python Perl TCL SVA Formal Verification Emulation Palladium Veloce SoC Architecture Fabric and Interconnect Verification
8+ yrs exp

Custom SOC IP Verification Engineer

Nvidia

Santa Clara, CA +1 18 days ago $168,000–$264,500
SystemVerilog UVM ASIC Verification NoC AMBA AXI CHI Python Perl TCL SVA Formal Verification Emulation Palladium Veloce SoC Architecture Scripting
6+ yrs exp

IP Verification Engineer

Amd

San Jose, CA +3 44 days ago $166,400–$249,600
System Verilog UVM Verilog ASIC Verification PCIe CXL NVMe Ethernet Python Perl FPGA HLS Computer Architecture Scripting Automation Simulation Tools
Hybrid