IP Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CASan Diego, CAAustin, TXLongmont, CO
Salary
$166,400–$249,600 / yr
Posted
70 days ago
Freshness
Confirmed live today
Closes
Aug 18, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $203k
This role $208k
$133k $262k
below market most similar roles pay here above market

This role pays more than 60% of similar roles. Most pay $168,500–$237,250 — the blue band above. At the midpoint, this role pays about $208k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · IP Verification Engineer

JOB TITLE: IP Verification Engineer As a Senior ASIC Verification Engineer within the front-end design and integration team, you will help bring to life cutting-edge FPGA and ASICs for various target customers. You will collaborate with architects, hardware engineers, and firmware engineers to understand new features for PCIe CXL based IPs. Your daily responsibilities include developing test plan documentation, coding IP or SS level UVM based testbenches including monitors, scoreboards, and checkers, and building directed and random verification tests. You will run regressions and debug test failures to ensure high design functional, performance, and implementation quality. Required skills include expertise in Verilog, SystemVerilog, Object Oriented programming, and UVM based verification frameworks. You must have experience with PCIe, CXL, NVMe, or ethernet protocols and proficiency in Python or Perl scripting.

What you'll do

  • Collaborate with architects and hardware engineers to understand new features for PCIe CXL based IPs.
  • Develop comprehensive test plan documentation covering hardware, firmware, and software driver use cases.
  • Code IP or subsystem level UVM based testbenches, including monitors, scoreboards, and checkers.
  • Build directed and random verification tests to validate design functionality.
  • Run regressions and debug test failures to ensure high design functional and performance quality.
  • Automate verification processes and flows using Python or Perl scripting.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Experience with PCIe, CXL, NVMe, or ethernet protocols.
  • Proficiency in IP level ASIC verification.
  • Expertise in Verilog, SystemVerilog, and Object Oriented programming.
  • Expertise in developing UVM based verification frameworks and testbenches.
  • Scripting and automation of verification processes and flows.
  • Experience working in a team environment through the ASIC/FPGA project lifecycle from planning to tape out.
  • Exposure to leadership or mentorship (preferred).

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