Custom SOC IP Verification Engineer

What you'll do

• Verify fabric and interconnect IP blocks as well as full chip integration including DMA, routing, arbitration, and flow control.
• Develop and implement UVM-based test plans for both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches for NoC topologies and multi-agent integrations.
• Drive the development of silicon and platform verification strategies for interconnect subsystems.
• Ensure compliance with industry-standard bus protocols such as AMBA AXI or CHI.
• Perform performance verification including bandwidth and latency analysis for interconnect fabrics.
• Execute assertion-based verification (SVA) to verify fabric and protocol properties.

What we're looking for

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 6+ years of experience in ASIC verification with a focus on fabric, interconnect, or network-on-chip at IP and full chip levels.
• Deep knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with industry-standard interconnect and bus protocols such as AMBA AXI or CHI.
• Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Proficiency in scripting languages including Python, Perl, or TCL.
• Knowledge of performance verification, bandwidth/latency analysis, and assertion-based verification (SVA).
• Experience with emulation platforms or verification IPs for bus protocols is desirable.