Custom SOC IP Verification Engineer

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 43 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $216k

$135k $278k

below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $216k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Custom SOC IP Verification Engineer

Role Posting Log in to save

The Senior Custom SOC/IP Verification Engineer joins the team to verify next-generation SoC and IP solutions. This role focuses on the ASIC design verification of fabric and interconnect IP blocks, as well as full chip integration. Key responsibilities include verifying DMA, routing, arbitration, ordering, flow control, and protocol compliance. The engineer will develop test plans and implement constrained-random and directed testbenches for network-on-chip topologies and multi-agent SoC integrations. Required technical skills include deep knowledge of SystemVerilog and UVM methodology, along with proficiency in Python, Perl, and TCL. The role requires expertise in industry-standard interconnect and bus protocols like AMBA AXI and CHI. The work involves ensuring robust connectivity and performance across complex SoC designs from IP bring-up through full chip integration.

Skills

SystemVerilog UVM ASIC Verification Network-on-Chip (NoC) AMBA AXI CHI Python Perl TCL SVA Formal Verification Emulation Palladium Veloce SoC Architecture DMA Flow Control Coherency

What you'll do

Perform ASIC design verification for fabric and interconnect IP blocks and full chip integration.
Verify DMA, routing, arbitration, ordering, flow control, and protocol compliance.
Develop and implement UVM-based test plans for IP-level and system-level scenarios.
Design and implement constrained-random and directed SystemVerilog testbenches for NoC topologies.
Drive the development of silicon and platform verification strategies for interconnect subsystems.
Execute verification plans to ensure first-time right performance and compliance across complex SoC designs.

What we're looking for

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
6+ years of experience in ASIC verification with a focus on fabric, interconnect, or network-on-chip verification.
Strong knowledge of SystemVerilog and UVM methodology.
Hands-on experience with industry-standard interconnect and bus protocols like AMBA AXI or CHI.
Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
Proficiency in scripting languages such as Python, Perl, or TCL.
Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics (preferred).
Experience in GPU or AI accelerator SoC interconnect verification is desirable (preferred).

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