Principal Design Verification Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $210,000–$310,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k

This role $260k

$134k most similar roles pay here $329k

This role pays more than 96% of similar roles. Most pay $164,600–$216,250 — the shaded band above. At the midpoint, this role pays about $260k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal Design Verification Engineer (Silicon Engineering)

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The Principal Design Verification Engineer role in Silicon Engineering at a leading tech company requires an experienced professional to lead and execute verification test plans for digital ASIC and FPGA designs at both block and system levels. This senior-level position involves developing comprehensive verification strategies, setting milestones, and ensuring thorough testing throughout the project lifecycle. Candidates should be proficient in Python for automation and possess strong experience with verification methodologies and tools. The ideal candidate will work on large-scale projects that demand meticulous attention to detail and a deep understanding of digital design principles.

Skills

Python ASIC verification FPGA verification

What you'll do

Lead and execute verification test plans for digital ASIC and FPGA projects.
Develop and manage verification milestones from project initiation to completion.
Conduct block-level and system-level verification tasks for complex designs.
Utilize Python for automation in the verification process.
Ensure adherence to U.S. Department of State ITAR requirements.

What we're looking for

Responsible for digital ASIC and FPGA verification at block and system level
Lead execution of verification test plans, development, and milestones
Strong Python skills for automation in verification processes
Extensive experience in design verification engineering
ITAR compliance adherence required for U.S. Department of State

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