Principal Design Verification Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$210,000–$355,000 / yr
Posted
113 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $282k
$117k most similar roles pay here $380k

This role pays more than 97% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $282k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal Design Verification Engineer

The Principal Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on providing reliable connectivity through the Starlink network by ensuring high-performance hardware functionality. The engineer is responsible for digital ASIC and FPGA verification at both block and system levels, leading test plan execution from inception to completion. Key responsibilities include pre-silicon verification, chip bring-up, and post-silicon validation of complex digital designs. To succeed, the candidate must possess expertise in UVM, OVM, or VMM methodologies, along with strong object-oriented programming and coding skills. The role requires proficiency in constrained random verification, coverage model implementation, and Python for automation. This position addresses critical hardware challenges to expand network capabilities in remote areas where connectivity was previously unavailable or unreliable.

What you'll do

  • Perform digital ASIC and FPGA verification at both block and system levels.
  • Lead and execute verification test plans from inception through completion.
  • Conduct pre-silicon verification for next-generation ASICs.
  • Execute chip bring-up and post-silicon validation processes.
  • Develop complex test benches to verify intricate digital designs.
  • Implement coverage models and analyze results to ensure design integrity.
  • Develop automation scripts using languages like Python to streamline verification tasks.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience with design verification and test bench development.
  • Experience with verification methodologies such as UVM, OVM, or VMM.
  • Strong object-oriented programming knowledge and coding skills.
  • Experience in constrained random verification.
  • Expertise in developing test plans, implementing coverage models, and analyzing results.
  • Experience with scripting languages like Python for automation.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.

More like this

Similar roles

Principal Design Verification Engineer

SpaceX

Redmond, WA 113 days ago $210,000$335,000
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Principal Design Verification Engineer

SpaceX

Irvine, CA 113 days ago $210,000$335,000
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Principal Design Verification Engineer

SpaceX

Austin, TX 113 days ago
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Design Verification Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 59 days ago $135,000$155,000
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp

Design Verification Engineer, Silicon Engineering

SpaceX

Redmond, WA 59 days ago $125,000$145,000
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp

Design Verification Engineer, Silicon Engineering

SpaceX

Irvine, CA 59 days ago $125,000$145,000
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp