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Hardware Security root-of-trust (RoT Secure Boot Firmware Resiliency Post-Quantum Cryptography AES-GCM SHA-2/3 LMS/XMSS ML-DSA/ML-KEM SPDM TCG DICE IEEE 802.1AR Open Compute Project (OCP) SONiC OpenBMC Caliptra OpenTitan OpenPRoT FPGA Bitstream Security Side-channel Analysis JTAG NIST SP 800-193 NSA CNSA 2.0 TPM +19 more Show less

Hardware Security Root of Trust Secure Boot Cryptographic Primitives ASIC FPGA Verilog SystemVerilog Python Bash NIST SP 800-193 CNSA 2.0 TCG DICE TPM Fault Injection Side-Channel Analysis JTAG PCB Layout Hardware Threat Modeling +14 more Show less

ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Python PyTorch TensorFlow LLM Machine Learning CI/CD Synthetic Data Drift Detection Observability Networking Data Contracts Deep Learning Production Monitoring +8 more Show less

Quantum Networking 3D CAD SolidWorks Creo Inventor RF Microwave Power Distribution Thermal Management Factory Acceptance Testing Site Acceptance Testing EIA-310 UL CE IEC Schematics +11 more Show less

Networking Security Cloud AI Infrastructure Routing Switching Wireless VPN Zero Trust Firewall High-Performance Fabrics Hybrid Cloud Telemetry Observability Lab Validation Performance Testing Interoperability Testing +12 more Show less

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

Kubernetes Python Go Terraform Ansible AI/ML Infrastructure GPU Clusters RoCE RDMA infrastructure-as-code Container Orchestration Networking Storage Observability Agile +10 more Show less

System Verilog UVM ASIC Design Verification Python Perl TCL Shell Scripts Verilog Formal Verification Veloce HAPS Ethernet UCIE UAL SPI I2C SerDes D2D PHY ODSP +14 more Show less

ASIC Package Design Signal Integrity (SI) Power Integrity (PI) High-Speed Routing Power Distribution Networks (PDN) EDA Tools Python Perl TCL Shell Programming Oscilloscopes TDR VNA Silicon Floor Planning Tapeout Hardware Development +11 more Show less

ASIC Signal Integrity Power Integrity SerDes SPICE Keysight ADS Ansys HFSS Cadence APD Python MATLAB IBIS Vector Network Analysis HBM UCIe CoWoS EMIB Transmission Line Theory Electromagnetics +13 more Show less

Systems Security Engineering Cybersecurity AI Machine Learning Embedded Systems Firmware C/C++ Python MATLAB AFSIM Risk Management Framework (RMF) Digital Signal Processing (DSP) Electronic Warfare Electronic Attack Intrusion Detection Vulnerability Assessment Open Architecture Standards Avionics Signal Spoofing Jamming +15 more Show less

C++ Python Go Java Kubernetes AWS GCP Azure CI/CD Bazel CMake GoogleTest Google Mock Catch2 Microservices Distributed Systems Dependency Injection +12 more Show less

C C++ RTOS VxWorks FreeRTOS ThreadX ARM Cortex-M PID Control Bare-metal Python MATLAB Git Jira Perforce Oscilloscope Logic Analyzer Optical Spectrum Analyzer +12 more Show less

C C++ Python Linux SONiC Device Driver Development I2C PCIe SPI MDIO TCP/IP Layer 2 Layer 3 ASIC Hardware Bring-up Secure-boot SFP QSFP +13 more Show less

C C++ RTOS VxWorks FreeRTOS ThreadX ARM Cortex-M ARM Cortex-R Bare-metal Python Shell Git Perforce Jira CI/CD I2C SPI UART MDIO DSP ASIC +16 more Show less

Go Python Kubernetes Distributed Systems Microservices OAuth 2.0 OIDC JWT mTLS gRPC Protobuf Kafka PostgreSQL Weaviate Milvus Qdrant OpenTelemetry Temporal LaunchDarkly SSE WebSockets zero-trust +17 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL +11 more Show less

Kubernetes AWS Azure GCP Terraform ArgoCD GitOps Infrastructure-as-Code SRE Service Mesh CNI Microservices Distributed Systems Observability Networking Hybrid Cloud On-premises +12 more Show less

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design +15 more Show less