This role pays more than
90%
of similar roles. Most pay
$173,450–$234,325
— the shaded band above.
At the midpoint, this role pays about
$262k
versus about
$204k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
222 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,200
across 171 roles with salary data.
Signal and Power Integrity Technical Leader will join the Cisco Silicon One team to lead the Silicon Packaging Signal and Power Integrity Team in developing next-generation ASIC packaging for various platforms. The role involves defining, designing, and verifying ASIC packaging while establishing design rules for ultra-high-speed signaling to meet power, performance, and area goals. Key responsibilities include analyzing substrate signal integrity and power integrity across interposers, substrates, and PCBs, as well as mentoring junior engineers and collaborating with system partners to resolve complex technical issues. The position requires expertise in 56G PAM4, high-speed SerDes architectures, channel modeling, and electromagnetics. Required tools and skills include Keysight ADS, Ansys HFSS/EM flow, Cadence APD, SPICE, MATLAB, Python scripting, Raptor-X, Vector Network Analysis, and IBIS. The work focuses on advanced IC package design for high-performance ASICs using 2.5D fanout technologies.
Lead the Silicon Packaging Signal and Power Integrity team to define and verify ASIC packaging for various platforms.
Develop and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB levels.
Design and document ASIC packages for high-volume release including post-layout extraction and reporting.
Resolve complex technical issues with system partners and vendors using advanced technology design rules.
Define processes, methods, and tools for the development of complex ASIC and package designs.
Participate in chip architecture discussions and review intricate IC and mixed-signal circuit designs.
Mentor junior engineers and foster a culture of design reviews and continuous improvement.
What we're looking for
Bachelor's degree in Electrical Engineering with 10+ years of experience, Master's with 8+ years, or PhD with 5+ years of signal/power integrity experience.
Experience with multiple high-speed ASIC tape-outs from a package perspective.
Expertise in 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.
Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
Experience with SPICE.
Experience leading small to medium technical teams (preferred).
Skilled in articulating technical concepts to diverse audiences both verbally and in writing (preferred).
Experience with advanced nodes, HBM, die-to-die interfaces, advanced packaging, MATLAB/Python, Raptor-X, Vector Network Analysis, or IBIS (preferred).
Signal Integrity
Power Integrity
Ansys HFSS
Keysight ADS
SI-Wave
Q3D
Polar
Matlab
VNA
TDR
SerDes
PCB Design
IC Package Design
electromagnetic-field theory
Transmission Line Theory
Linux