Hardware Security Technical Leader

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Raleigh, NC
Salary
$139,200–$201,400 / yr
Employment
Full-time
Posted
1 day ago
Freshness
Confirmed live today
Closes
Nov 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $170k
$128k $246k
below market most similar roles pay here above market

This role pays less than 68% of similar roles. Most pay $158,950–$227,300 — the blue band above. At the midpoint, this role pays about $170k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Hardware Security Technical Leader

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The Hardware Security Technical Leader CSDL Hybrid joins the Hardware & Firmware Security Team within the Security & Trust Organization. This role serves as a technical leader and security partner to hardware engineering teams, bridging the gap between security assessments and practical hardware implementation. You will analyze hardware architectures from system levels down to ASICs, FPGAs, and discrete components to identify vulnerabilities and design-in resilience. Key responsibilities include interpreting industry standards like NIST SP 800-193 and CNSA 2.0 into engineering requirements, providing technical mentorship, and authoring security documentation. Required skills include hardware design, low-level architecture, cryptographic primitives, and secure boot. Preferred competencies include Python, Bash, Verilog, SystemVerilog, and experience with hardware threat modeling, side-channel analysis, and AI-assisted development for hardware security applications.

Skills

Hardware Security Root of Trust Secure Boot Cryptographic Primitives ASIC FPGA Verilog SystemVerilog Python Bash NIST SP 800-193 CNSA 2.0 TCG DICE TPM Fault Injection Side-Channel Analysis JTAG PCB Layout Hardware Threat Modeling

What you'll do

  • Provide actionable design guidance to hardware teams to achieve HW-CSDL compliance.
  • Deconstruct hardware architectures from system level down to ASICs and components to identify vulnerabilities.
  • Translate industry and government security standards into practical engineering requirements and technical guidance.
  • Author high-quality security requirements, reference architectures, and implementation guides for engineering audiences.
  • Lead and manage multiple parallel security initiatives and consulting engagements across diverse product families.
  • Provide technical mentorship to members of the Security and Trust engineering team.
  • Educate hardware design communities to foster a security-first culture throughout the product development lifecycle.

What we're looking for

  • Degree in Electrical/Computer Engineering or related field.
  • 9+ years of experience for BS holders, 6+ years for MS holders, or 3+ years for PhD holders.
  • Prior experience leading security initiatives and mentoring engineers as a technical leader.
  • Prior background in hardware development including interpreting schematics, block diagrams, datasheets, PCB layouts, or register-level documentation.
  • Prior background in hardware security fundamentals like Root of Trust, Secure Boot, resiliency, cryptographic primitives, or secure key storage.
  • Experience with AI-assisted development and automation for hardware security applications (preferred).
  • Experience with scripting (Python, Bash) and RTL design/verification (Verilog, SystemVerilog) for hardware security solutions (preferred).
  • Experience with hardware security frameworks, standards (NIST SP 800-193, CNSA 2.0, TCG DICE/TPM), or threat modeling (preferred).

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