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C C++ SystemVerilog Python Perl Ruby FPGA HAPS Xilinx JTAG Logic Analyzers Oscilloscopes UART AMBA AXI AHB APB SPI I2C I3C USB Assembly Linker Scripts Makefile +19 more Show less

Generative AI LLM Python C/C++ Perl SystemVerilog UVM Assertions Model Context Protocol AWS GCP Azure OCI CI/CD Jenkins GitHub Actions Git Perforce Object-Oriented Programming +14 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up +9 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Scripting +10 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up +9 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up +9 more Show less

ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design +8 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage +9 more Show less

DRC LVS PERC ESD Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT tapeout Advanced Nodes Rule Deck Validation +14 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

DRC LVS ESD PERC Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile Physical Design tapeout DFT SerDes DDR Advanced Nodes +15 more Show less

DRC LVS ESD PERC Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT RDL tapeout Advanced Nodes AI Agents +15 more Show less