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SystemVerilog UVM Verilog C++ C SystemC TLM RTL ASIC Verification Linux Windows Perl Ruby Shell Scripting Makefiles HLS Simulation Graphics Pipeline Architecture +13 more Show less

System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Metric-Driven Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal NoC Silicon Debug Regression Management +13 more Show less

Firmware Validation SoC Validation Pre-silicon Verification C C++ Python Perl Bash Simics BIOS UEFI ACPI PCIe CXL MCTP SPDM PLDM RAS TPM Secure Boot Virtualization SR-IOV Generative AI GitHub Copilot +19 more Show less

Generative AI LLM Python C/C++ SystemVerilog UVM Assertions Model Context Protocol (MCP) CI/CD AWS GCP Azure OCI Jenkins GitHub Actions Git Perforce Object-Oriented Programming (OOP) Data Mining +14 more Show less

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification +9 more Show less

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification +9 more Show less

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification +9 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design +10 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification +9 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage +8 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

DRC LVS PERC ESD Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile DFT SerDes DDR Physical Design Flow Tapeout Hard IP Integration +15 more Show less

ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design +11 more Show less

ASIC Physical Verification DRC LVS ESD PERC Calibre ICV Pegasus SoC Design Python TCL Perl Bash Makefile DFT SerDes DDR Hard IP Integration Tapeout +15 more Show less

DRC LVS PERC ESD Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile DFT SerDes DDR Physical Design Flow Tapeout Rule Deck Validation +15 more Show less