Senior Full Chip Physical Verification Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Palo Alto, CAAustin, TXIrvine, CASunnyvale, CA
Salary: $175,000–$280,000 / yr
Posted: 179 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $228k

$135k $296k

below market most similar roles pay here above market

This role pays more than 81% of similar roles. Most pay $176,493–$218,375 — the blue band above. At the midpoint, this role pays about $228k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Senior Full Chip Physical Verification Engineer

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The Sr. Full Chip Physical Verification Engineer joins the Silicon Engineering team to develop next-generation silicon for space and ground infrastructures. This role involves owning and executing full-chip DRC, LVS, ESD, PERC, and antenna signoff for advanced node SoCs. You will develop and optimize physical verification flows, interpret foundry Design Rule Manuals, and debug complex violations across hierarchical designs. Key responsibilities include performing ESD verification, coordinating tapeout readiness across block and top-level teams, and leveraging AI agents to automate rule deck validation and violation triage. Required skills include proficiency with Calibre, ICV, or Pegasus, along with scripting in csh/bash, Perl, Python, TCL, and Makefile. The work focuses on solving connectivity problems for the Starlink satellite constellation using large SoC designs exceeding 10M gates.

Skills

DRC LVS PERC ESD Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile DFT SerDes DDR Physical Design Flow Tapeout Rule Deck Validation

What you'll do

Execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
Develop, maintain, and optimize physical verification flows for advanced node SoCs.
Interpret foundry Design Rule Manuals and translate rule updates into verified flow changes.
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
Perform ESD verification to validate protection strategies and CDM/HBM compliance.
Coordinate signoff across block and top-level teams to drive tapeout readiness.
Engage with foundry teams to resolve DRM ambiguities and manage waiver requests.
Leverage AI agents to automate rule deck validation and violation triage workflows.

What we're looking for

Bachelor’s degree in electrical engineering, computer engineering, or computer science.
5+ years of ASIC and/or physical design flow development experience in industry.
Ability to work extended hours and weekends as needed to meet critical project milestones.
U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
Experience and deep understanding of SOC top level physical design flows (preferred).
Experience in IP integration such as memories, I/Os, analog IPs, SerDes, or DDR (preferred).
Deep expertise in DRC, LVS, PERC, and ESD verification methodologies (preferred).
Hands-on proficiency with Calibre, ICV, or Pegasus (preferred).