Senior Staff Pre Silicon Verification Engineer

Amd

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$200,000–$300,000 / yr
Posted
10 days ago
Freshness
Confirmed live yesterday
Closes
Sep 22, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $250k
$134k most similar roles pay here $318k

This role pays more than 90% of similar roles. Most pay $176,600–$227,900 — the shaded band above. At the midpoint, this role pays about $250k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 474 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 474 roles with salary data.

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At a glance

TL;DR · Senior Staff Pre Silicon Verification Engineer

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Senior Staff Pre Silicon Verification Engineer The Adaptive and Embedded Computing Group seeks a Senior Staff Pre Silicon Verification Engineer to provide technical leadership in the verification of cutting-edge DRAM Memory Controller IPs, high-speed Crypto, and Network-on-Chip designs. You will architect, develop, and utilize simulation and formal-based verification environments at both block and SoC levels to ensure first-pass silicon success. Responsibilities include managing verification teams, developing comprehensive testbenches, and collaborating with architecture and software teams to define strategies. The role requires expertise in UVM, SystemVerilog, assertion-based verification, and metric-driven verification. You will work with tools such as Synopsys VCS, Cadence Xcelium, and formal property checking tools like JasperGold or Questa Formal. The core work involves solving complex hardware challenges related to DDR5, LPDDR6, HBM4 protocols, board skew, jitter modeling, and power-aware verification for high-performance VLSI designs.

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