Design Verification Engineer, Silicon Engineering

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$135,000–$155,000 / yr
Posted
59 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $145k
$124k most similar roles pay here $236k

This role pays less than 85% of similar roles. Most pay $162,750–$214,000 — the shaded band above. At the midpoint, this role pays about $145k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Design Verification Engineer, Silicon Engineering

Role Posting Log in to save

Design Verification Engineer (Silicon Engineering) will join cross-disciplinary teams to develop next-generation ASICs for space and ground infrastructure. The role focuses on digital ASIC verification at both the block and system levels, where the engineer is responsible for writing and reviewing test plans, developing test harnesses, and creating SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies. Day-to-day tasks include executing test plans, running regressions, achieving code and functional coverage closure, and automating test case generation. The candidate will contribute to pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs. Required skills include proficiency in SystemVerilog, Python, MATLAB, and object-oriented programming. This role addresses the technical challenge of building high-performance hardware components to enable reliable broadband connectivity through a large satellite constellation.

Skills

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up

What you'll do

  • Perform digital ASIC verification at both block and system levels.
  • Write and review test plans while developing test harnesses and sequences.
  • Develop SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Automate test case generation using Python and MATLAB programs.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Verify complex digital designs independently as a hands-on self-starter.

What we're looking for

  • Bachelor's degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Experience with verification methodologies such as UVM.
  • Strong object-oriented programming knowledge and coding skills.
  • Proficiency in scripting languages like Python and MATLAB for automation.
  • Experience in constrained random verification and coverage model analysis.
  • Experience with RTL design, chip bring-up, and post-silicon validation.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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