Design Verification Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$135,000–$155,000 / yr
Posted
105 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $145k
$123k $247k
below market most similar roles pay here above market

This role pays less than 93% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $145k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

The Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on digital ASIC verification at the block and system levels to expand the performance of the Starlink network. Key responsibilities include writing and reviewing test plans, developing SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies, and executing regressions to achieve code and functional coverage closure. The engineer will also automate test case generation and contribute to pre-silicon verification, chip bring-up, and post-silicon validation. Required technical skills include experience with design verification, testbench development, and object-oriented programming. Candidates should possess proficiency in Python and MATLAB for automation, along with knowledge of constrained random verification and RTL design.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification

What you'll do

  • Perform digital ASIC verification at both the block and system levels.
  • Write and review comprehensive test plans, test harnesses, and test sequences.
  • Develop SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Automate test case generation using Python and MATLAB programs.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Execute all necessary steps to fully verify complex digital designs.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM (preferred).
  • Strong object-oriented programming, coding, and problem-solving skills (preferred).
  • Experience with RTL design, chip bring-up, post-silicon validation, and scripting languages like Python (preferred).

Related searches

More Design Verification Engineer jobs Design Verification Engineer jobs in Palo Alto All jobs at SpaceX

More like this

Similar roles

Design Verification Engineer

SpaceX

Redmond, WA 105 days ago $125,000–$145,000
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save

Design Verification Engineer

SpaceX

Irvine, CA 105 days ago $125,000–$145,000
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save

Design Verification Engineer

SpaceX

Austin, TX 105 days ago
ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification
1+ yrs exp
Save

Principal Design Verification Engineer

SpaceX

Palo Alto, CA +4 159 days ago $210,000–$355,000
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save

Principal Design Verification Engineer

SpaceX

Redmond, WA +3 159 days ago $210,000–$335,000
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save

Principal Design Verification Engineer

SpaceX

Irvine, CA +3 159 days ago $210,000–$335,000
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
Save