Design Verification Engineer

SpaceX

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$125,000–$145,000 / yr
Posted
105 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $135k
$112k $248k
below market most similar roles pay here above market

This role pays less than 96% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $135k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on digital ASIC verification at the block and system levels to expand the performance of the Starlink network. Key responsibilities include writing and reviewing test plans, developing SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies, and executing regressions to achieve code and functional coverage closure. The engineer will also automate test case generation and contribute to pre-silicon verification, chip bring-up, and post-silicon validation. Required skills include proficiency in SystemVerilog, Python, and MATLAB, along with experience in constrained random verification and object-oriented programming. The work addresses the technical challenge of providing reliable broadband connectivity in previously inaccessible locations.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

Skills

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification

What you'll do

  • Perform digital ASIC verification at both the block and system levels.
  • Write and review comprehensive test plans, test harnesses, and test sequences.
  • Develop SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Automate test case generation using Python and MATLAB programs.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Execute all necessary steps to fully verify complex digital designs.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM (preferred).
  • Strong object-oriented programming, coding, and problem-solving skills (preferred).
  • Experience with RTL design, chip bring-up, post-silicon validation, and scripting languages like Python (preferred).

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