Design Verification Engineer

SpaceX

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Work type
On-site
Location
Austin, TX
Posted
105 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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Similar $199k
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This listing doesn't post a salary. Most similar roles pay $168,500–$229,100.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructures. This role focuses on digital ASIC verification at both the block and system levels to expand the performance and capabilities of the Starlink network. Key responsibilities include writing and reviewing test plans, developing SystemVerilog testbench infrastructure using UVM and non-UVM methodologies, and executing test plans to achieve code and functional coverage closure. The engineer will also automate test case generation and contribute to pre-silicon verification, chip bring-up, and post-silicon validation. Required skills include experience with design verification, testbench development, and object-oriented programming. Candidates should also possess proficiency in Python and MATLAB for automation, along with knowledge of constrained random verification and RTL design.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

ASIC Verification SystemVerilog UVM Python MATLAB RTL Design Post-Silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Pre-Silicon Verification

What you'll do

  • Perform digital ASIC verification at both the block and system levels.
  • Write and review comprehensive test plans, test harnesses, and test sequences.
  • Develop SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Automate test case generation using Python and MATLAB programs.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Execute all necessary steps to fully verify complex digital designs independently.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM (preferred).
  • Strong object-oriented programming, problem-solving, and coding skills (preferred).
  • Experience in constrained random verification, developing test plans, and implementing coverage models (preferred).
  • Experience with scripting languages like Python, RTL design, chip bring-up, and post-silicon validation (preferred).

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