Design Verification Engineer, Silicon Engineering

SpaceX

Confirmed live 2 days ago Low trust

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Work type
On-site
Location
Austin, TX
Posted
59 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Similar $189k
$130k most similar roles pay here $236k

This listing doesn't post a salary. Most similar roles pay $164,687–$214,250.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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TL;DR · Design Verification Engineer, Silicon Engineering

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As a Design Verification Engineer (Silicon Engineering), you will join cross-disciplinary teams to develop next-generation ASICs for deployment in space and ground infrastructures. You will be responsible for digital ASIC verification at both the block and system levels, where you will write and review test plans, develop test harnesses, and create test sequences. Your daily work involves developing SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies to test designs including DSP blocks. You will execute test plans, run regressions, and achieve code and functional coverage closure while automating test case generation using Python and MATLAB programs. This role involves pre-silicon verification, chip bring-up, and post-silicon validation for the Starlink network. Required skills include object-oriented programming, constrained random verification, RTL design knowledge, and proficiency in scripting languages to solve complex hardware challenges.

Skills

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Scripting

What you'll do

  • Perform digital ASIC verification at both block and system levels.
  • Write and review test plans while developing test harnesses and sequences.
  • Develop SystemVerilog testbench infrastructure using both UVM and non-UVM methodologies.
  • Execute test plans, run regressions, and achieve code and functional coverage closure.
  • Automate test case generation using Python and MATLAB programs.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Verify complex digital designs independently as a hands-on self-starter.

What we're looking for

  • Bachelor's degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Experience with verification methodologies such as UVM.
  • Strong object-oriented programming knowledge and coding skills.
  • Experience with constrained random verification and coverage models.
  • Proficiency in scripting languages like Python for automation and MATLAB.
  • Experience in RTL design, chip bring-up, and post-silicon validation.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for export control authorizations.

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