Senior Full Chip Physical Verification Engineer

SpaceX

Confirmed live today Low trust

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Work type
On-site
Location
Austin, TXIrvine, CASunnyvale, CA
Posted
179 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

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TL;DR · Senior Full Chip Physical Verification Engineer

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Sr. Full Chip Physical Verification Engineer (Silicon Engineering) joins the Silicon Engineering team to develop next-generation silicon for space and ground infrastructures. The engineer will own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff for advanced node SoCs. Key responsibilities include developing and optimizing physical verification flows, interpreting foundry Design Rule Manuals, debugging complex violations across hierarchical designs, and driving tapeout readiness. The role requires coordinating signoff across block and top-level teams while leveraging AI agents to automate rule deck validation and violation triage. Candidates must possess expertise in Calibre, ICV, or Pegasus, along with proficiency in csh/bash, Perl, Python, TCL, and Makefile. This work directly enables global connectivity by solving complex integration requirements for large SoC designs exceeding 10M gates.

Skills

ASIC Physical Verification DRC LVS ESD PERC Calibre ICV Pegasus SoC Design Python TCL Perl Bash Makefile DFT SerDes DDR Hard IP Integration Tapeout

What you'll do

  • Execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
  • Develop, maintain, and optimize physical verification flows for advanced node SoCs.
  • Interpret foundry Design Rule Manuals and translate rule updates into verified flow changes.
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
  • Perform ESD verification to validate protection strategies and CDM/HBM compliance.
  • Coordinate signoff across block and top-level teams to drive tapeout readiness.
  • Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Leverage AI agents to automate rule deck validation and violation triage workflows.

What we're looking for

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of ASIC and/or physical design flow development experience in industry.
  • Ability to work extended hours and weekends as needed to meet critical project milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for required U.S. Department of State authorizations.
  • Experience and deep understanding of SOC top level physical design flows (preferred).
  • Experience in IP integration such as memories, I/Os, analog IPs, SerDes, or DDR (preferred).
  • Deep expertise in DRC, LVS, PERC, and ESD verification methodologies (preferred).
  • Hands-on proficiency with Calibre, ICV, or Pegasus (preferred).

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