Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

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Work type
On-site
Location
Austin, TX
Posted
today

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

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TL;DR · Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Senior Full Chip Physical Verification Engineer position available in Austin, TX for a silicon engineering team. This role involves executing full-chip DRC, LVS, ESD, PERC, and antenna signoff using tools like Calibre, ICV, or Pegasus, developing and optimizing verification flows for advanced node SoCs, interpreting foundry Design Rule Manuals, debugging complex violations, coordinating tapeout readiness across teams, and leveraging AI to automate workflows. Candidates should have deep expertise in SOC top-level physical design flows, IP integration, DRC/LVS methodologies, and experience with large SOC designs at 4nm nodes or below. Proficiency in scripting languages such as csh/bash, Perl, Python, TCL, and Makefile is required, along with a strong ability to work collaboratively in a dynamic environment.

What you'll do

  • Own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
  • Develop and optimize physical verification flows for advanced node SoCs.
  • Interpret foundry Design Rule Manuals (DRM) to implement rule updates in verification flows.
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
  • Coordinate tapeout readiness by managing signoff processes across block, top-level, and hard IP design teams.

What we're looking for

  • Extensive experience in full-chip physical design flows and IP integration.
  • Proficient in DRC, LVS, PERC, ESD verification methodologies at advanced nodes.
  • Hands-on expertise with Calibre, ICV, or Pegasus for physical verification.
  • Direct experience interpreting and implementing foundry Design Rule Manuals (DRM).
  • Experience with large SOC designs (>10M gates) and frequencies > 1GHz.
  • Strong scripting skills in csh/bash, Perl, Python, TCL, Makefile.

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