Senior Full Chip Physical Verification Engineer

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
133 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $194k
$141k most similar roles pay here $235k

This listing doesn't post a salary. Most similar roles pay $171,500–$216,250.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior Full Chip Physical Verification Engineer

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Sr. Full Chip Physical Verification Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation silicon for space and ground infrastructure. The role involves owning and executing full-chip DRC, LVS, ESD, PERC, and antenna signoff while developing and optimizing physical verification flows for advanced node SoCs. Key responsibilities include interpreting foundry Design Rule Manuals, resolving complex violations across hierarchical designs, performing ESD verification to ensure compliance, and coordinating tapeout readiness with block and top-level teams. The candidate will utilize industry standard tools such as Calibre, ICV, or Pegasus, while leveraging AI agents for automated rule deck validation and triage. Required skills include proficiency in scripting languages like Python, TCL, Perl, and Bash. The work focuses on high-performance SoC designs exceeding 10M gates at advanced nodes to enable global connectivity.

Skills

DRC LVS ESD PERC Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile Physical Design tapeout DFT SerDes DDR Advanced Nodes

What you'll do

  • Execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus.
  • Develop, maintain, and optimize physical verification flows for advanced node SoCs.
  • Interpret foundry Design Rule Manuals (DRM) and translate rule updates into verified flow changes.
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
  • Perform ESD verification to validate protection strategies and ensure CDM/HBM compliance.
  • Coordinate signoff across block and top-level teams to drive tapeout readiness.
  • Engage directly with foundry teams to resolve DRM ambiguities and manage waiver requests.
  • Automate rule deck validation, violation triage, and reporting workflows using AI agents.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in ASIC and/or physical design flow development.
  • Proficiency with industry standard tools such as Calibre, ICV, or Pegasus.
  • Expertise in DRC, LVS, PERC, and ESD verification methodologies.
  • Experience interpreting and implementing foundry Design Rule Manuals (DRM).
  • Experience with advanced nodes at 4nm and below for large SoC designs.
  • Strong scripting skills in csh, bash, Perl, Python, TCL, or Makefile.
  • Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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