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Physical Design CAD Tools Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI SoC Design Signoff Physical Verification +9 more Show less

Verilog SystemVerilog Python TCL Perl VHDL Spice Power Analysis Formal Verification DRC LVS RC Extraction Machine Learning Data Analysis DFT Library Characterization EDA Tools +12 more Show less

Verilog SystemVerilog Python TCL Perl VHDL Spice Power Analysis Formal Verification DRC LVS RC Extraction Machine Learning Data Analysis DFT Library Characterization EDA Tools +12 more Show less

AI machine learning Python Perl TCL VLSI SoC Design RTL Synthesis Place-and-Route Power Analysis Software Testing Algorithm Design +8 more Show less

ASIC Design RTL Synthesis Static Timing Analysis Physical Design Power Analysis Python TCL EDA Tools VLSI PPA Optimization Formal Verification AI Agents LLM Data Analytics Design Infrastructure DFT +11 more Show less

Power Analysis Power Modeling Power Optimization ASIC SoC RTL AI ML Silicon Validation Physical Design Architecture Workload-driven Analysis Automation Semiconductor Design +9 more Show less

Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT +20 more Show less

Python C++ VLSI EDA AI ML LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design Package Design HPC +11 more Show less

DFT VLSI Power Analysis Thermal Analysis IR Drop RTL STA ATE SLT Applied ML Gen AI Post-Silicon Debug +7 more Show less

C++ Verilog RTL Design ASIC Design Python Perl Make Synthesis Verification Algorithms +5 more Show less

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design Emulation Synthesis Place and Route Timing Closure SoC Architecture Kernel Debuggers Bus Protocols DDR NoC +14 more Show less

RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure +20 more Show less

DFX ASIC SoC DFT Scan ATPG MBIST Python RTL Silicon Bring-up Verification APIs Data Analytics Automation VLSI +10 more Show less

Python Tcl ML Frameworks Physical Design P&R Timing Analysis IR/Signal-EM Power and Noise Analysis Back-end Verification Chip Floorplan Power and Clock Distribution PPA +7 more Show less

Silicon Bring-up Silicon Validation Python C/C++ DFT SoC Architecture Lab Automation Oscilloscopes Logic Analyzers Power Analyzers Root-Cause Analysis PVT Sign-off Regression Frameworks AI Tools LLM-assisted Debug RAS DPPM +12 more Show less

DTCO Synthesis PnR EM/IR STA Physical Verification Cadence Innovus Synopsys Fusion Compiler Python Tcl Perl machine-learning PPA Analysis SoC Design CMOS Design Space Exploration +11 more Show less

Python C++ Perl Ruby Go Shell Scripting Docker Kubernetes OpenShift GNU Make CI/CD Linux Agentic AI RTL Design SoC Design DevOps Build Automation +12 more Show less

RTL Design SoC Architecture Digital Logic Power Analysis Power Modeling Hardware Emulation Python Low-Power Design power-management RTL Simulation Verification SoC Power Methodology +7 more Show less

Python C++ Perl EDA Tools Innovus Fusion Compiler Crosscheck Virtuoso VLSI Physical Design Library Modeling Data Pipelines AI ML LLM Dashboards Synthesis Place and Route Timing Closure Power Analysis +15 more Show less

ASIC Design SoC Design Verilog SystemVerilog C++ Python Perl Tcl Synopsys Fusion Compiler Data Structures Algorithms Build Infrastructure RTL Agentic AI Claude Code Cursor +11 more Show less