Senior Emulation Performance Methodology & Debug Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $121,800–$182,600 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Closes: Apr 14, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k

This role $152k

$107k $260k

below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $174,375–$233,050 — the blue band above. At the midpoint, this role pays about $152k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Senior Emulation Performance Methodology & Debug Engineer

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The Senior Emulation Performance Methodology & Debug Engineer joins the Emulation Team within the central SoC digital hardware organization. This role focuses on the development and support of SoC pre-silicon platforms, specifically handling the design, development, and deployment of uniform global methodologies for emulation build generation and debug across various FPGA based platforms. The engineer will perform pre-silicon prototyping for new SoC designs, including hardware and software bring-up, and debug low-level software and hardware issues. Key technical requirements include expertise in Verilog, SystemVerilog, C, Python, and TCL. Candidates must demonstrate proficiency in Veloce, Palladium, and Xilinx/Intel FPGAs, while managing synthesis, place and route, and timing closure for SoC building blocks like CPU/DSP cores, DDR, and bus protocols.

Skills

Verilog SystemVerilog Python TCL C FPGA Veloce Palladium JTAG ASIC Design Emulation Synthesis Place and Route Timing Closure SoC Architecture Kernel Debuggers Bus Protocols DDR NoC

What you'll do

Design and deploy global methodologies for emulation build generation and debug across FPGA platforms.
Perform pre-silicon prototyping for new SoC designs, including enablement and bring-up.
Bring up new FPGA emulation and prototyping hardware and software.
Debug low-level software and hardware issues using JTAG and kernel debuggers.
Validate and debug digital circuits and SoC building blocks like interconnects and peripherals.
Execute synthesis, place and route, and timing closure for emulation platforms.
Generate waveforms and provide content debug support for system debugging.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
5+ years of experience working in emulation and silicon environments (preferred).
Experience with emulation platforms (FPGA Prototyping, Veloce, Palladium) and tools like Synthesis, Place and Route, and Timing Closure (preferred).
Expertise in Verilog, SystemVerilog, and C programming (preferred).
Proficiency in Python and TCL scripting (preferred).
Experience with Xilinx/Intel FPGAs, JTAG, kernel debuggers, and SoC architectures (preferred).

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