Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

Samsung Electronics

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$180,200–$270,400 / yr
Employment
Full-time
Posted
15 days ago
Freshness
Confirmed live today
Closes
Dec 31, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $225k
$136k $285k
below market most similar roles pay here above market

This role pays more than 67% of similar roles. Most pay $164,438–$232,000 — the blue band above. At the midpoint, this role pays about $225k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 85 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

The Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology joins the Global Advanced Technology Enablement team to drive technology development across the System LSI business. This role involves building highly efficient design and analysis flows and methodologies to push the power, performance, and area envelope for next-generation SoC products. Key responsibilities include developing CAD flows for custom design, exploring methodologies for low-power and high-performance goals, and collaborating with IP development teams to ensure process technology and design rules are consumable. The position requires expertise in synthesis, PnR, EM/IR, STA, and physical verification using Cadence Innovus and Synopsys Fusion Compiler. Candidates must possess strong skills in Tcl, Perl, and Python, along with knowledge of CMOS fundamentals, device physics, and machine-learning practices for improving productivity.

What you'll do

  • Build highly efficient design and analysis flows and methodologies for DTCO.
  • Drive collaboration with IP development teams to ensure process technology and design rules are consumable.
  • Develop CAD flows for custom design to push the PPA envelope on aggressive designs.
  • Explore methodologies to achieve low-power and high-performance goals for Samsung-specific SoC design styles.
  • Solve CAD and design methodology-related challenges by creating analysis methodologies and metrics.
  • Provide and maintain thorough documentation and publish results for project management needs.
  • Analyze large data sets to deduce information and apply learnings to various design scenarios.

What we're looking for

  • Must have a Bachelor’s in Computer Science/Engineering with 10+ years of experience, a Master’s with 8+ years, or a Ph.D. with 6+ years.
  • Must have 10+ years of experience in custom design tools and methodology development.
  • Must have 10+ years of experience with industry standard automated design tools for synthesis, PnR, EM/IR, STA, and physical verification.
  • Must have 10+ years of experience with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.
  • Must have strong knowledge of CMOS fundamentals, device physics, scaling trends, and design challenges at advanced technology nodes.
  • Must have strong skills in scripting/programming languages like Tcl, Perl, and Python.
  • Must have strong data analysis skills to analyze and deduce information from large data sets.
  • Experience with foundries is a plus (preferred).
  • Experience in improving productivity or quality through machine-learning practices is preferred (preferred).
  • Applicants must be authorized to access information subject to U.S. export control laws.

More like this

Similar roles

Senior DTCO Engineer, CPU Physical Design

Nvidia

Santa Clara, CA +3 8 days ago $136,000–$218,500
CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding
5+ yrs exp

ASIC DTCO, Timing and Technology Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
ASIC Design DTCO STA Hspice Finesim PrimeSim AFS Spectre PT-SI Tempus Genus Innovus Python Perl TCL Unix Shell C/C++ ML Modeling RTL to GDS PPA Analysis
4+ yrs exp

Design for Test Engineer

Apple Inc

Cupertino, CA 54 days ago $146,717–$218,000
Verilog RTL DFT ATPG STA MBIST JTAG Python Perl VCS NCSIM Gate-level Simulation Silicon Diagnosis ATE Low-power Design ECOs
2+ yrs exp