Senior DFT Power Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $216k

$133k most similar roles pay here $279k

This role pays more than 78% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior DFT Power Methodology Engineer

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As a Senior DFT Power Methodology Engineer, you will join the Design-for-X Engineering team to innovate in the areas of DFT Power, Thermal, and Voltage Noise. You will develop groundbreaking low power and thermal solutions for manufacturing tests on complex semiconductor chips while partnering with multi-functional teams like Product Development and Power Architecture. Your daily responsibilities include performing post-silicon data analysis for power, architecting next-generation solutions, and deploying DFT methodologies using Applied ML and Gen AI tools. You will also mentor junior engineers on test designs and trade-offs regarding cost and quality. Required skills include expertise in VLSI areas such as timing and IR Drop, proficiency with statistical tools for data analysis, and experience in silicon debug on ATE or SLT platforms. You must be able to utilize AI coding harnesses to solve complex problems.

Skills

DFT VLSI Power Analysis Thermal Analysis IR Drop STA RTL Silicon Debug ATE SLT EDA Statistical Tools

What you'll do

Innovate in DFT Power, Thermal, and Voltage Noise Methodology areas for manufacturing tests.
Develop low power and thermal solutions for datacenter GPUs operating at extreme conditions.
Perform post-silicon data analysis to architect next-generation power solutions.
Develop and deploy DFT methodologies using Applied ML and Gen AI solutions.
Mentor junior engineers on test designs, cost trade-offs, and quality improvements.
Solve complex problems regarding outgoing chip quality in collaboration with multi-functional teams.

What we're looking for

A BSEE with experience, an MSEE with , or a PhD with experience in DFT design and power is required.
Candidates must have an understanding of fundamental DFT topics and VLSI areas including power, timing, and voltage noise.
Experience with Power Analysis, Thermal Analysis, and IR Drop tools is preferred.
Experience applying AI for EDA-related problem-solving is preferred.
Proficiency in using statistical tools for data analysis and insights is required.
Candidates should have exposure to multi-functional areas including RTL, clock design, STA, place-n-route, and power.
Experience in silicon debug and bring-up on ATE or SLT platforms is required.
Ability to think like a programmer to translate actions into AI coding harnesses is required.

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