Senior DFT Power Methodology Engineer

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $216k

$136k $278k

below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $166,811–$216,587 — the blue band above. At the midpoint, this role pays about $216k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior DFT Power Methodology Engineer

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The Senior DFT Power Methodology Engineer joins the Design-for-X Engineering team to innovate in DFT Power, Thermal, and Voltage Noise Methodology areas. This role involves developing groundbreaking low power and thermal solutions for manufacturing tests on complex datacenter GPUs. Key responsibilities include performing post-silicon data analysis for power, architecting next-generation solutions, and deploying DFT methodologies using Applied ML and Gen AI solutions. The engineer will also mentor junior staff on test designs and trade-offs. Required skills include expertise in DFT design, VLSI power, timing, and voltage noise, along with knowledge of Power Analysis, Thermal Analysis, and IR Drop tools. Candidates should possess experience in RTL, clocks design, STA, place-n-route, and silicon debug on ATE or SLT platforms while utilizing statistical tools for data analysis.

Skills

DFT VLSI Power Analysis Thermal Analysis IR Drop RTL STA ATE SLT Applied ML Gen AI Post-Silicon Debug

What you'll do

Innovate in DFT Power, Thermal, and Voltage Noise methodology areas.
Develop low power and thermal solutions for manufacturing tests on datacenter GPUs.
Implement new methodologies to solve complex problems and improve outgoing chip quality.
Perform post-silicon data analysis for power to architect next-generation solutions.
Develop and deploy DFT methodologies using Applied ML and Gen AI solutions.
Mentor junior engineers on test designs, costs, and technical trade-offs.

What we're looking for

BSEE with experience in DFT design and power.
MSEE with experience in DFT design and power.
PhD with 6+ years of experience in DFT design and power.
Understanding of fundamental DFT topics and VLSI areas of power, timing, and voltage noise.
Excellent knowledge in using statistical tools for data analysis and insights.
Good exposure to multi-functional areas including RTL and clocks design, STA, place-n-route, and power.
Experience in Silicon debug and bring-up on the ATE or SLT platforms.
Experience in Power Analysis, Thermal Analysis & IR Drop tools (preferred).
Experience in application of AI for EDA-related problem-solving (preferred).
Outstanding written and oral communication skills (preferred).
Experience in managing DFT Power Methodology for designs (preferred).
Experience in post-silicon debug for thermal & IR Drop (preferred).
Strong collaborative and interpersonal skills with a proven ability to guide and influence (preferred).

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