Senior EDA Engineer, SOC Design Methodology

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k

This role $177k

$123k most similar roles pay here $258k

This role pays less than 62% of similar roles. Most pay $168,500–$227,862 — the shaded band above. At the midpoint, this role pays about $177k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior EDA Engineer, SOC Design Methodology

Role Posting Log in to save

As a Senior EDA Engineer, SOC Design Methodology, you will join a cross-functional team focused on developing software to automate SoC design and build flows for ASIC engineers. You will be responsible for building new methodologies and tools to achieve Speed of Light design goals while partnering with design and verification engineers to identify workflow gaps. Additionally, you will co-develop EDA tool capabilities with vendors to improve project execution. The role requires proficiency in Verilog or SystemVerilog along with strong programming skills in C++, Python, Perl, or Tcl. Candidates should possess a solid understanding of computer algorithms and data structures. You will work within the domain of SoC design, RTL, and build infrastructure to solve technical bottlenecks in chip design by creating tools that improve speed and reliability for complex integrated circuits.

Skills

Verilog SystemVerilog C++ Python Perl Tcl SoC Design ASIC Design RTL Data Structures Algorithms Synopsys Fusion Compiler AI Coding Tools Claude Code Cursor

What you'll do

Develop software to automate SoC design and build flows for ASIC engineers.
Build new methodologies and tools to achieve "Speed of Light" in ASIC design.
Identify and resolve workflow gaps by partnering with design and verification engineers.
Co-develop EDA tool capabilities with external vendors to meet internal design needs.
Create tools that improve the reliability and speed of chip design processes.
Implement software solutions across SoC design, RTL, and build infrastructure.

What we're looking for

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
3+ years of EDA tool development experience in the ASIC or SoC design field.
Hands-on experience with ASIC or SoC design and verification.
Proficiency in Verilog or SystemVerilog.
Strong programming skills in C++, Python, Perl, or Tcl.
Solid understanding of computer algorithms and data structures.
Experience with SoC integration including IP connectivity, clock/reset automation, or top-level design flow.
Familiarity with Synopsys Fusion Compiler or similar next-generation design tools.

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