Senior EDA Engineer, SOC Design Methodology

Nvidia

Confirmed live today Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Employment: Full-time
Posted: 20 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior EDA Engineer, SOC Design Methodology

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JOB TITLE: Senior EDA Engineer, SOC Design Methodology The Senior EDA Engineer, SOC Design Methodology joins a cross-functional team focused on developing software that powers how ASIC engineers design chips. This role involves building tools, automating flows, and co-developing EDA tool capabilities with vendors to achieve Speed of Light design methodology. The engineer will develop software to automate SoC design and build flows, enabling ASIC engineers to work faster and more reliably while identifying workflow gaps. Key responsibilities include partnering with design and verification engineers to support project execution. Required technical skills include proficiency in Verilog or SystemVerilog and strong programming in C++, Python, Perl, or Tcl. Candidates must understand computer algorithms, data structures, and ASIC or SoC design and verification. Experience with SoC integration and Synopsys Fusion Compiler is also relevant.

Skills

ASIC Design SoC Design Verilog SystemVerilog C++ Python Perl Tcl Synopsys Fusion Compiler Data Structures Algorithms Build Infrastructure RTL Agentic AI Claude Code Cursor

What you'll do

Develop software to automate SoC design and build flows for ASIC engineers.
Build new methodologies and tools to achieve ASIC design at Speed of Light.
Partner with design and verification engineers to identify and bridge workflow gaps.
Co-develop EDA tool capabilities with external vendors to meet specific design needs.
Support project execution by improving the reliability and speed of design processes.
Create tools to resolve bottlenecks in the chip design lifecycle.

What we're looking for

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
3+ years of EDA tool development experience in the ASIC or SoC design field.
Hands-on experience with ASIC or SoC design and verification.
Proficiency in Verilog or SystemVerilog.
Strong programming skills in C++, Python, Perl, or Tcl.
Solid understanding of computer algorithms and data structures.
Experience with SoC integration, IP connectivity, clock/reset automation, or top-level design flow (preferred).
Familiarity with Synopsys Fusion Compiler or similar next-generation design tools (preferred).

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