Senior VLSI Methodology Engineer

Nvidia

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 20 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $196k

This role $177k

$124k $244k

below market most similar roles pay here above market

This role pays less than 57% of similar roles. Most pay $176,650–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior VLSI Methodology Engineer

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The Senior VLSI Methodology Engineer joins the team to design automation infrastructure powering library modeling, quality checks, and release for PD flows. The role involves building scalable systems, including validation pipelines and dashboards, to perform quality checking for GPU and SOC libraries. Key responsibilities include developing automated library analysis, validation, and quality control flows while collaborating with process and cell-design teams to enhance cell design methodologies and apply adaptive threshold partitioning. The position requires hands-on experience with industry-standard EDA tools such as Innovus, Fusion Compiler, Crosscheck, and Virtuoso. Candidates must possess advanced Python, C++, or Perl skills to develop data-driven pipelines for collection, validation, and reporting. The work focuses on library modeling, abstraction, and data integrity for advanced nodes in silicon design.

Skills

Python C++ Perl EDA Tools Innovus Fusion Compiler Crosscheck Virtuoso VLSI Physical Design Library Modeling Data Pipelines AI ML LLM Dashboards Synthesis Place and Route Timing Closure Power Analysis

What you'll do

Build scalable systems for quality checking GPU and SOC libraries.
Develop automated library analysis, validation, and quality control flows using EDA tools.
Integrate library quality systems and enhance cell design methodologies with design teams.
Apply adaptive threshold partitioning to improve cell design methodologies.
Define and implement guidelines for library modeling, abstraction, and data integrity.
Build and integrate data-driven pipelines and verification systems for PD flows.
Develop automated dashboards to track critical metrics like release readiness and validation pass rates.

What we're looking for

M.S. in Electrical Engineering or related field or equivalent experience.
4+ years of Library, Physical Design, and/or CAD methodology experience.
Hands-on development with industry-standard EDA tools including Innovus, Fusion Compiler, Crosscheck, Virtuoso, or similar.
Advanced Python, C++, or Perl skills with experience in workflow automation and data pipelines.
Understanding how library models are consumed in chip design flows (preferred).
2+ years in library modeling/validation, quality systems, or physical design automation (preferred).
Experience building robust library models with system-level quality and automation (preferred).
Applied AI/ML/LLM experience to enhance EDA tools, automation, or design methodologies (preferred).

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