below marketmost similar roles pay hereabove market
This role pays less than
60%
of similar roles. Most pay
$177,250–$229,100
— the blue band above.
At the midpoint, this role pays about
$194k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The Standard Cell Design Methodology & Flow Engineer joins the custom circuits team to support processor design efforts using deep submicron technologies. This role involves developing standard cell library designs and serving as the primary interface between internal CAD teams and foundries regarding production flows and PDK requirements. Key responsibilities include implementing sophisticated digital blocks in Verilog or SystemVerilog, running simulations or formal checks for verification, and utilizing data analysis or Machine Learning models to study circuit trends in timing, power, and area. The engineer must collaborate with technology teams on process requirements and flow automation. Required skills include proficiency in Python, TCL, and Perl, alongside experience with Spice simulation, static timing analysis, Liberty formats, and various EDA tools for synthesis, place-route, and library characterization.
Interface with internal CAD teams to plan production flows and coordinate PDK requirements with the foundry.
Work with technology teams to define new process requirements and enable relevant design tools and flows.
Implement sophisticated digital blocks using Verilog or SystemVerilog.
Run simulations or formal checks to verify digital block designs.
Use data analysis and Machine Learning models to study circuit trends in timing, power, and area.
Detect quality issues within large datasets using automated data analysis techniques.
Automate standard cell development and integration flows using Python, TCL, or Perl.
Perform library characterization, including timing, power, and noise modeling.
What we're looking for
BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc. (preferred)
Experience with timing modeling of large custom macros and complex sequential flops (preferred).
Exposure to Design For Test, scan concept and write DFT friendly RTL (preferred).
Understands all aspects of implementation specification, design, timing, power, and flow automation (preferred).
Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation (preferred).
Flow automation skills in standard cells development and integration using Python/TCL/Perl (preferred).