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UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

RTL Design ASIC Design Microarchitecture CPU GPU NoC Cache Coherency Physical Design Silicon +5 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing +9 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects SOC Simulation Verification Environments Post-processing +8 more Show less

RTL NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration SoC Front-end Synthesis +10 more Show less

RTL NoC SoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Directory-based Coherence Memory Hierarchy Crossbars Arbitration Scripting Front-end Synthesis +11 more Show less

System Verilog UVM RTL Design Python Perl Formal Verification AMBA AXI ACE CHI Microarchitecture Cache Coherence Data Structures Algorithms Object-Oriented Programming +10 more Show less

Verilog System Verilog RTL Design C C++ Python Perl x86 ARM Digital Design DFT MMU High-Speed Design +8 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols +7 more Show less

RTL NoC SoC Synthesis STA CDC Lint MESI MOESI Directory-based coherence Cache Coherency Memory Hierarchy Crossbars Arbitration Scripting +10 more Show less

RTL NoC ASIC Design Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration Front-end Synthesis +9 more Show less

RTL ASIC Design NoC Synthesis STA CDC Lint Cache Coherency MESI MOESI Memory Hierarchy Crossbars Arbitration SoC Scripting +10 more Show less

RTL NoC Crossbars Cache Coherency MESI MOESI Directory-based Coherence Synthesis STA CDC Lint Memory Hierarchy SoC Front-end Synthesis +9 more Show less

Cable and Harness Design Electrical Schematic Capture Capital Harness Xpedition PADS DC Power Distribution Grounding Shielding Connector Selection Change Management Root-Cause Investigation MS Office DITMCO Test Engineering Electrical Engineering +10 more Show less

3D CAD Design for Manufacturability Design for Assembly Signal Integrity Antenna Design Inductive Power Transfer Geometric Tolerancing Statistical Tolerance Analysis Magnet Array Design Consumer Electronics Mandarin +6 more Show less

SystemVerilog UVM Unix Perl Git UPF Gate-level Simulation Formal Verification LPDDR SoC +5 more Show less

Verilog VHDL ASIC Design Flow RTL Design AMBA ACE AXI CHI STA DFT ECO Python Perl Logic Synthesis Timing Analysis Floor-planning Memory Controller Coherent Interconnect Cache Design On-chip Network Topologies +15 more Show less

Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture +6 more Show less

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Performance Analysis Power Optimization Chiplets +10 more Show less