Design Verification Engineer, Fabric Interconnect

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
11 days ago
Freshness
Confirmed live today
Closes
Apr 13, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $152k
$87k $245k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $152k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer, Fabric Interconnect

The Design Verification Engineer - Fabric Interconnect joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the integration-level verification of Fabric Top, specifically addressing coherency, PCIe/CXL traffic, and configuration access traffic for cloud hardware. The engineer will develop UVM and System Verilog based verification environments, run and debug simulations, and interact with partner IP and SOC teams to define test plans. Key responsibilities include leveraging automation, formal-based methods, and generative AI solutions to improve verification efficiency. The position requires technical expertise in protocols such as CHI and AMBA, as well as experience with fabric interconnects, virtualization, and security. The work directly supports the development and manufacturing of state-of-the-art computer chips for cloud infrastructure.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

What you'll do

  • Own integration-level verification of Fabric Top, including coherency, PCIe/CXL traffic, and configuration access traffic.
  • Define verification strategies and test plans in coordination with partner IP, SOC, and VIP teams.
  • Develop UVM and System Verilog based verification environments at the integration level.
  • Run and debug simulations to drive hardware quality and identify issues.
  • Utilize automation, formal-based methods, and generative AI solutions to enhance the verification toolkit.
  • Innovate new methodologies and tools to improve overall verification efficiency.
  • Coach and mentor team members in specific areas of technical expertise.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Ability to provide proof of citizenship or US residency for access to export-controlled information.
  • Experience leading verification of designs using Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols (preferred).
  • Experience in fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges (preferred).
  • Experience driving IP verification from definition to silicon, including test plans, debugging, and coverage signoff (preferred).
  • Experience with UVM, System Verilog, Python, and applying generative AI to verification tasks (preferred).

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