This role pays more than
70%
of similar roles. Most pay
$168,500–$234,825
— the shaded band above.
At the midpoint, this role pays about
$223k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
512 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 512 roles with salary data.
As an Interconnect Micro-architect/RTL Design Engineer on the Infinity Fabric Architecture and RTL team, you will develop the next generation of coherent interconnects to provide connectivity between CPUs, GPUs, and special purpose accelerators. Your daily responsibilities include early architectural and performance exploration through micro-architectural definition, optimizing designs for power, performance, area, and timing, and writing synthesizable Verilog RTL. You will also perform unit level testing, create assertions for coverage analysis, produce block level documentation, and participate in post-silicon functional and performance debugging. The role requires expertise in Verilog, SystemVerilog, C, C++, and scripting languages like Perl or Python. You must possess a strong understanding of digital electronics, high-speed designs, multi-processor coherency, memory ordering, and cache systems while addressing complex interconnect challenges across diverse markets including servers, high-performance computing, and machine intelligence.
Perform early architectural and performance exploration through micro-architectural definition and design.
Optimize designs to meet specific power, performance, area, and timing requirements.
Write readable and synthesizable Verilog RTL code for coherent interconnects.
Conduct unit level testing to deliver high-quality code to the Design Verification Team.
Create assertions to improve coverage and analyze design coverage points.
Produce well-written block level design documentation.
Participate in post-silicon functional and performance debug and tuning.
What we're looking for
Experience as an RTL design engineer with strong communication and problem-solving skills.
Ability to write readable, synthesizable Verilog RTL and create block-level documentation.
Capability to perform architectural exploration, optimization for PPA (power, performance, area), and post-silicon debugging.
Bachelor's, Master's, PhD, or equivalent practical experience in Electrical Engineering, Computer Engineering, or a related technical field (preferred).
Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs (preferred).
Excellent knowledge of Verilog and System Verilog (preferred).
Working knowledge of C, C++, and scripting languages like Perl or Python (preferred).
Understanding of digital electronics, high-speed designs, multi-processor coherency, and memory ordering (preferred).