ASIC Design Engineer, Fabric/Interconnect

As an ASIC Design Engineer – Fabric/Interconnect, you will join a team focused on developing high-quality components for System on Chip designs. You will be responsible for the design and integration of coherent and non-coherent fabrics into subsystems, requiring a deep understanding of on-chip interconnect architectures such as NoC topologies, crossbars, and arbitration. Your daily work involves owning all aspects of RTL development, including design, templating, scripting, and RTL generation while integrating shared IP blocks to optimize memories and hard macros. You will collaborate with front-end synthesis, STA, power, performance, and functional verification teams to ensure timing goals and high quality are met. The role requires expertise in memory hierarchy, cache coherency protocols like MESI or MOESI, and familiarity with lint, CDC, and synthesis tools to solve complex interconnect challenges.