Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

Confirmed live yesterday High trust

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $151,000–$251,800 / yr
Posted: 21 days ago
Freshness: Confirmed live yesterday
Closes: Dec 31, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k

This role $201k

$139k most similar roles pay here $264k

This role pays less than 51% of similar roles. Most pay $171,125–$240,000 — the shaded band above. At the midpoint, this role pays about $201k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 58 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Micro-architect/Logic Designer, Coherent Interconnect

Role Posting Log in to save

Micro-architect/Logic Designer, Coherent Interconnect will join the System IP team to lead micro-architecture development for custom coherent interconnect IP and last level cache blocks. The role involves driving RTL design, performance and power optimization, logic debug, and timing closure while collaborating with system architects, verification, and physical design teams. Candidates must possess expertise in Verilog, ASIC design flows including synthesis, DFT, and STA, as well as experience with scripting languages like Perl or Python. Technical requirements include knowledge of AMBA5 CHI, AMBA4 ACE, and AXI protocols, along with familiarity with mesh, ring, and crossbar on-chip network topologies. The position focuses on developing high-performance memory subsystems and coherent cache designs to solve complex problems in high-performance digital systems, ensuring the delivery of scalable, power-optimized IP for integration into various semiconductor products.

Skills

RTL Verilog VHDL AMBA CHI ACE AXI ASIC Design Flow Logic Synthesis DFT STA ECO Python Perl Memory Controller Cache Design Coherent Interconnect

What you'll do

Lead the micro-architecture development for custom coherent interconnect IP and last level cache blocks.
Drive RTL design, performance optimization, and power optimization for critical coherent interconnect components.
Develop detailed specifications from early high-level architectural exploration through to final technical documentation.
Perform logic debug and ensure timing closure during the physical design and implementation phases.
Collaborate with verification teams to ensure functionality and correctness of the hardware designs.
Work with physical design and CAD teams to resolve area and timing constraints.
Mentor junior engineers and provide guidance on technical projects within the team.

What we're looking for

Must have a Bachelor’s degree with 6+ years of experience, a Master’s with 4+ years, or a PhD with 2+ years.
Must possess a strong background in RTL design for coherent interconnects, memory controllers, or last level cache blocks.
Required expertise in Verilog and deep understanding of the full ASIC design flow including synthesis, verification, and timing analysis.
Knowledge of system caches and directory snoop filter protocols is required.
Familiarity with on-chip network topologies such as mesh, ring, and crossbar is required.
Knowledge of Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols is required.
Experience in leading and mentoring a team of engineers is required.
Must be authorized to access information subject to U.S. export control laws.

Similar roles

CPU Micro-architect

Samsung Electronics

Remote (San Jose, CA) 21 days ago $124,000–$208,400

CPU Microarchitecture Arm ISA x86 RISC-V Verilog C++ Python TLB Branch Prediction Pipelining Multi-core Systems SpecInt17 GB6

4+ yrs exp Remote

Save

Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 177 days ago $136,000–$218,500

Verilog RTL ASIC Design Flow Logic Synthesis Timing Closure Computer Architecture Cache Coherency high speed interconnects DFT Floor-planning ECO Lab Debug

5+ yrs exp Hybrid

Save

Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Santa Clara, CA 51 days ago $168,000–$264,500

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Power Optimization Performance Analysis Chiplets NVLINK-C2C

8+ yrs exp Hybrid

Save

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 32 days ago $136,000–$218,500

Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture

5+ yrs exp

Save

NoC Interconnect Design Engineer and Architect

Qualcomm

San Diego, CA 43 days ago $115,600–$173,400

NoC AHB AXI CHI RTL ASIC Design Synthesis STA Lint FPGA Post-Silicon Debug CPU Architecture VLSI Design Power Analysis Micro-architecture

2+ yrs exp

Save

NoC Interconnect Design Engineer and Architect

Qualcomm

San Diego, CA 15 days ago $98,500–$147,700

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting SoC IC Package Circuit Design

Save