Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$151,000–$251,800 / yr
Posted
5 days ago
Closes
Sep 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $201k
$139k most similar roles pay here $264k

This role pays more than 50% of similar roles. Most pay $177,250–$223,700 — the shaded band above. At the midpoint, this role pays about $201k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 41 open roles on FindRole.

Listed pay typically runs $175,000–$222,500 across 40 roles with salary data.

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At a glance

TL;DR · Micro-architect/Logic Designer, Coherent Interconnect

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As a Micro-Architect/Logic Designer at Samsung Austin Research and Development Center’s Advanced Computing Lab, you will lead the development of custom coherent interconnect IP and last level cache blocks, collaborating closely with system architects, verification teams, and performance engineers to ensure timely delivery. Your day-to-day responsibilities include defining next-generation interconnects, conducting microarchitecture research, verifying design functionality, optimizing RTL for power and performance, and mentoring junior team members. The ideal candidate has extensive experience in Verilog and ASIC design flow, including RTL design, verification, synthesis, and timing analysis, with a strong background in high-performance digital designs. Familiarity with Arm AMBA5 CHI, ACE, or AXI protocols, memory subsystems, and on-chip network topologies is essential. This role offers the opportunity to work within Samsung’s System IP team, which develops proprietary interconnect solutions for market-leading products, focusing on performance optimization and use-case-driven analysis in a dynamic global environment.

Skills

Verilog VHDL Perl Python STA DFT ECO AMBA5_CHI AMBA4_ACE AXI coherent_interconnect memory_controller cache_design mesh_topology ring_topology crossbar_topology RTL_design ASIC_design_flow logic_synthesis prototyping bring-up&_lab_debug

What you'll do

  • Drive the development of custom coherent interconnect IP and last level cache blocks.
  • Define next-generation Samsung coherent interconnects and LLC with architects.
  • Develop microarchitecture specifications from high-level exploration to detailed design.
  • Verify functionality and correctness of designs with verification teams.
  • Achieve timing and area goals in collaboration with implementation teams.
  • Produce quality RTL code on schedule, meeting PPA (performance-power-area) targets.

What we're looking for

  • 10+ years of experience in RTL design for high-performance digital designs or equivalent education.
  • Strong background in owning and driving the development of coherent interconnect IP and last level cache blocks.
  • Expertise in Verilog and deep understanding of ASIC design flow including verification, synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
  • Experience leading and mentoring a team of engineers in a dynamic global environment.

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