below marketmost similar roles pay hereabove market
This role pays less than
60%
of similar roles. Most pay
$177,287–$254,750
— the blue band above.
At the midpoint, this role pays about
$201k
versus about
$216k
for comparable roles.
Based on 240 similar postings.
Employer
About Samsung Electronics
Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.
Samsung Electronics currently has
94 open roles
on FindRole.
Listed pay typically runs
$106,000–$174,500
across 85 roles with salary data.
JOB TITLE: Micro-architect/Logic Designer, Coherent Interconnect
As a Micro-architect/Logic Designer within the System IP team, you will lead the micro-architecture development of custom coherent interconnect IP and last level cache blocks. You will drive RTL design, performance and power optimization, and logic debug while collaborating with system architects, verification, and physical design teams. Your daily work involves performing microarchitecture research, defining detailed specifications, and producing quality RTL to meet PPA goals. You must possess expertise in Verilog, ASIC design flows, and protocols including AMBA5 CHI, AMBA4 ACE, and AXI. The role requires knowledge of memory subsystem design, directory snoop filter protocols, and on-chip network topologies like mesh, ring, and crossbar. You will solve complex problems regarding architecture scalability for high-performance digital designs and memory subsystems.
Lead the micro-architecture development of custom coherent interconnect IP and last level cache blocks.
Drive the RTL design, performance optimization, and power optimization for coherent interconnect components.
Perform micro-architecture research and develop detailed specifications from early high-level architectural exploration.
Produce high-quality RTL code that meets specific power, performance, and area (PPA) goals.
Execute logic debug and timing closure for the design in coordination with physical design and CAD teams.
Verify the functionality and correctness of the design in partnership with the verification team.
Mentor junior engineers and help shape the technical culture of the team.
What we're looking for
6+ years of experience with a Bachelor’s degree, 4+ years with a Master’s, or 2+ years with a PhD in a relevant technical field.
Strong background in RTL design for coherent interconnects, memory controllers, or LLC for high-performance digital designs.
Demonstrated experience in architectural through RTL design for high-performance digital designs.
Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
Knowledge of system caches, directory snoop filter protocols, and on-chip network topologies like mesh, ring, and crossbar.
Knowledge of Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols.
Experience in leading and mentoring a team of engineers.
Applicants must be authorized to access information subject to U.S. export control laws.