Staff Design Verification Engineer

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
163 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $233k
$136k most similar roles pay here $282k

This role pays more than 76% of similar roles. Most pay $168,500–$233,050 — the shaded band above. At the midpoint, this role pays about $233k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff Design Verification Engineer

Staff Design Verification Engineer - Coherent Interconnect will join the team to support the development of the Neoverse Coherent Mesh Network, a scalable and configurable system interconnect used in networking infrastructure, storage, server, high performance compute, AI, and industrial solutions. The role involves building and maintaining detailed verification plans and strategies while collaborating with architects and designers to debug and develop new features. Key responsibilities include architecting and developing efficient SystemVerilog/UVM based test benches, designing new stimulus and coverage, debugging functional regression failures, and driving improvements in verification methodology. Required expertise includes CPU microarchitecture knowledge of cache coherence, memory systems, and bus protocols like AMBA CHI or ACE. Candidates should possess experience with SystemVerilog/UVM constrained-random testbenches, while additional skills may include PCIe, Compute Express Link, Formal Verification techniques, and scripting languages such as Python or Perl.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

See salary data

What you'll do

  • Build and maintain detailed verification plans and strategies for the CMN interconnect.
  • Architect and develop efficient SystemVerilog/UVM based test benches.
  • Design new stimulus and coverage to ensure product quality.
  • Debug functional regression failures and close coverage gaps.
  • Develop and drive improvements in the existing verification methodology.
  • Work with architects and designers to debug and develop new features.

What we're looking for

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • 8+ years of hands-on experience in verification or RTL design.
  • Experience with CPU microarchitecture including cache coherence, memory systems, and bus protocols like AMBA CHI or ACE.
  • Experience in the specification, creation, and debugging of SystemVerilog/UVM constrained-random testbenches.
  • Applied knowledge and experience in PCIe or Compute Express Link (preferred).
  • Experience in Formal Verification techniques or scripting languages such as Python or Perl (preferred).

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