Staff Design Verification Engineer, Network Coherent Interconnect

Arm Holdings

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $198,100–$268,000 / yr
Posted: 20 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k

This role $233k

$136k $282k

below market most similar roles pay here above market

This role pays more than 76% of similar roles. Most pay $171,500–$230,087 — the blue band above. At the midpoint, this role pays about $233k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

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At a glance

TL;DR · Staff Design Verification Engineer, Network Coherent Interconnect

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Staff Design Verification Engineer - Network Coherent Interconnect The design verification team is seeking a Staff Design Verification Engineer to support the development of the next generation of the NI-700 Non-Coherent Network-on-Chip Interconnect. This role involves the specification, creation, and debug of System Verilog and UVM constrained-random testbenches to validate highly scalable interconnects. The engineer will work on products optimized for ArmV8 and ArmV9 processors across mobile, networking, storage, and automotive domains. Key responsibilities include verifying multiprocesssing microarchitecture, including cache coherence and bus protocols such as AMBA5 CHI, AMBA4 ACE, or AXI. Candidates must possess software engineering skills in object-oriented programming, data structures, and algorithms, alongside proficiency in scripting languages like Python or Perl. Experience with Formal Verification testbenches is also considered a plus for this technical role.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

Skills

System Verilog UVM RTL Design Python Perl Formal Verification AMBA AXI ACE CHI Microarchitecture Cache Coherence Data Structures Algorithms Object-Oriented Programming

What you'll do

Design and verify the next generation of Arm NI-700 Non-Coherent Network-on-Chip Interconnects.
Create and debug System Verilog and UVM constrained-random testbenches.
Validate multiprocess microarchitecture features including cache coherence and bus protocols like AMBA5 CHI, AMBA4 ACE, or AXI.
Develop and maintain verification environments using object-oriented programming, data structures, and algorithms.
Write and execute scripts using Python or Perl to support verification tasks.
Perform formal verification on testbenches to ensure design correctness.

What we're looking for

Hold a Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science.
Have 8+ years of experience in verification or RTL design.
Possess multiprocesssing microarchitecture experience including knowledge of cache coherence and bus protocols like AMBA5 CHI, AMBA4 ACE, or AXI.
Have experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
Demonstrate software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
Have excellent knowledge of scripting languages such as Python or Perl.
Experience in Formal Verification testbenches is a plus (preferred).

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