Senior Design Verification Engineer, Fabric Interconnect

Microsoft

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Hybrid

Quick summary

Work type: Hybrid
Location: —
Salary: $119,800–$234,700 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Closes: Apr 13, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $177k

$106k $248k

below market most similar roles pay here above market

This role pays less than 60% of similar roles. Most pay $177,250–$216,587 — the blue band above. At the midpoint, this role pays about $177k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

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At a glance

TL;DR · Senior Design Verification Engineer, Fabric Interconnect

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The Senior Design Verification Engineer - Fabric Interconnect joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the integration-level verification of Fabric Top, specifically addressing coherency, PCIe/CXL traffic, and configuration access traffic. The engineer will develop UVM and System Verilog based verification environments, run simulations to drive quality, and collaborate with partner IP and SOC teams to define test plans. Key responsibilities include leveraging automation, formal-based methods, and generative AI solutions to improve verification efficiency. The position requires expertise in CHI and AMBA protocols, as well as experience with fabric interconnects, virtualization, and security. The work involves solving complex hardware manufacturing and quality challenges for state-of-the-art computer chips used in cloud infrastructure.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing

What you'll do

Lead integration-level verification of Fabric Top, including coherency, PCIe/CXL traffic, and configuration access traffic.
Develop UVM and System Verilog based verification environments at the integration level.
Run and debug simulations to ensure hardware quality and drive verification closure.
Define verification strategies and test plans in coordination with partner IP, SOC, and VIP teams.
Utilize automation, formal-based methods, and generative AI solutions to improve verification efficiency.
Innovate new methodologies and tools to optimize the verification toolkit.
Coach and mentor team members in specific areas of technical expertise.

What we're looking for

Obtain a Doctorate with 1+ years of experience, a Master's with 4+ years, or a Bachelor's with 5+ years of technical engineering experience.
Pass the Microsoft Cloud Background Check and meet all government security screening requirements.
Provide proof of citizenship, US residency, or other protected status for export-controlled information access.
Develop UVM/System Verilog based verification environments at the integration level and run/debug simulations.
Own or lead integration-level verification of Fabric Top, including coherency, PCIe/CXL traffic, and configuration access traffic.
Leverage automation, formal-based methods, and AI-based approaches to improve verification efficiency (preferred).
Demonstrate expertise in CHI and AMBA protocols, as well as fabric interconnects, coherency, virtualization, or PCIe/CXL (preferred).
Experience driving IP verification from definition to silicon, including test plans, debugging, and coverage signoff (preferred).

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