Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
97 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $216k
$137k $278k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $177,250–$223,000 — the blue band above. At the midpoint, this role pays about $216k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Design Engineer, Coherent High Speed Interconnect

Role Posting Log in to save

The Senior Design Engineer, Coherent High Speed Interconnect will join the Coherent High Speed Interconnect team to work on the architecture and design of state-of-the-art high speed coherent interconnects for mobile SoCs and GPUs. The role involves collaborating with architects, external partners, software engineers, and circuit designers to deliver class leading high speed coherent interconnects. Key responsibilities include architecture, RTL design, performance analysis, and power optimization. Candidates must possess strong working knowledge of Verilog or System Verilog and experience with Link layer stacks, including Data link and Physical layers. Useful expertise includes industry standard interconnect protocols like PCIE, CXL, AXI, and CHI, as well as SerDes and memory technologies like DDR and LPDDR. This work enables the creation of integrated products built via chiplets.

Skills

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Performance Analysis Power Optimization Chiplets

What you'll do

  • Design and architect state-of-the-art high-speed coherent interconnects for mobile SoCs and GPUs.
  • Develop NVLINK-C2C technology to enable coherent interconnection of GPUs, DPUs, and CPUs via chiplets.
  • Perform RTL design using Verilog or System Verilog for interconnect components.
  • Conduct performance analysis and power optimization for high-speed interconnect systems.
  • Implement link layer stacks including Data Link and Physical layers.
  • Integrate interconnect protocols such as PCIe, CXL, AXI, and CHI into hardware designs.
  • Mentor junior engineers and interns on design processes and technical standards.

What we're looking for

  • BS or equivalent experience in Electrical Engineering, Computer Engineering, or a related degree is required.
  • Advanced degrees such as an MS or PhD are preferred.
  • 8+ years of relevant design experience is required.
  • Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, and CHI is useful.
  • Experience with Link layer stacks, including Data link layer and Physical layer, is required.
  • Experience with physical layer interconnects such as Memory (DDR, LPDDR), PCIE, and SerDes is required.
  • Experience and knowledge in architecture, RTL design, performance analysis, and power optimization are required.
  • Strong working knowledge of Verilog or System Verilog is required.
  • Good communication and interpersonal skills are required.
  • A history of mentoring junior engineers and interns is preferred.

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