Senior Design Engineer, Coherent High Speed Interconnect

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 51 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $216k

$137k most similar roles pay here $278k

This role pays more than 72% of similar roles. Most pay $172,375–$224,175 — the shaded band above. At the midpoint, this role pays about $216k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Design Engineer, Coherent High Speed Interconnect

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As a Senior Design Engineer, Coherent High Speed Interconnect, you will join the Coherent High Speed Interconnect team to focus on the architecture and design of state-of-the-art high speed coherent interconnects for mobile SoCs and GPUs. You will collaborate with architects, external partners, software engineers, and circuit designers to deliver class leading high speed coherent interconnects that enable integrated products built via chiplets. This role involves solving technical challenges related to connecting GPUs, DPUs, and CPUs with custom silicon. To succeed, you must possess expertise in Verilog or System Verilog, along with experience in RTL design, performance analysis, and power optimization. You should have knowledge of industry standard interconnect protocols like PCIe, CXL, AXI, and CHI, as well as experience with link layer stacks, SerDes, and memory interfaces such as DDR and LPDDR.

Skills

Verilog System Verilog RTL Design PCIe CXL AXI CHI SerDes DDR LPDDR Link Layer Physical Layer Power Optimization Performance Analysis Chiplets NVLINK-C2C

What you'll do

Design and architect state-of-the-art high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs.
Develop chiplet-based integrated products to enable coherent interconnection between GPUs, DPUs, and CPUs.
Perform RTL design using Verilog or SystemVerilog for high-speed interconnect components.
Conduct performance analysis and power optimization for high-speed interconnect architectures.
Implement link layer stacks including data link and physical layers for various protocols.
Integrate industry standard interconnect protocols such as PCIe, CXL, AXI, and CHI into designs.
Manage the physical layer of interconnects including Memory (DDR/LPDDR), PCIe, and SerDes.

What we're looking for

BS degree in Electrical Engineering, Computer Engineering, or a related field is required.
Advanced degrees such as an MS or PhD are preferred.
Candidates must have at least 8 years of relevant design experience.
Knowledge of industry standard interconnect protocols like PCIe, CXL, AXI, and CHI is useful.
Experience with link layer stacks including Data Link and Physical layers is required.
Experience with physical layer interconnects such as Memory (DDR, LPDDR), PCIe, and SerDes is required.
Proficiency in architecture, RTL design, performance analysis, and power optimization is required.
Strong working knowledge of Verilog or SystemVerilog is required.

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