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UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

IC Packaging RF Design HFSS Momentum Signal Integrity Power Integrity FCBGA FCCSP WLCSP QFN Machine Learning Automation SERDES Thermal Simulation S-parameters Impedance Matching +11 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

Electrical Engineering PCB Design Mentor Graphics xDX PSpice MATLAB LabVIEW Python Circuit Simulation Configuration Management Troubleshooting +5 more Show less

Mechanical Design Technical Documentation Procurement Physics Mathematics

RFIC ASIC Design Cadence Virtuoso ADS LNA PLL 4G 5G 6G WLAN GPS Electro Magnetic simulation Neural Networks Physical Verification +10 more Show less

VHDL UVM FPGA ASIC CPLD Intel Quartus Lattice Diamond Microsemi Libero Mentor Graphics Expedition PCIe AXI SERDES DMA MIL-STD-1553 DO-254 System on Chip High Speed Data Interfaces +12 more Show less

Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL +6 more Show less

Physical Design Floorplanning Synthesis Placement Routing Clock Tree Synthesis Static Timing Analysis Physical Verification Formal Equivalence Power Optimization IR-drop Electromigration EDA Tools Low Power Verification +9 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

Mechanical Engineering MATLAB ANSYS Monte Carlo Methods Design Controls Risk Management Reliability Engineering New Product Development (NPD) Statistical Analysis Modeling Simulation Engineering Analysis Data Analysis +8 more Show less

NX SolidWorks Creo Teamcenter ASME Y14.5 GD&T FEA Abaqus ANSYS CAD PLM PDM DFM DFA CNC Machining Injection Molding Thermal Management +12 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

ASIC RTL to GDS Flow Virtuoso Circuit Design Synthesis Place and Route System Simulation Design Verification Scripting +4 more Show less

SolidWorks NX Creo Teamcenter ASME Y14.5 GD&T FEA CAD PLM PDM DFM DFA 3/5-axis CNC Machining Injection Molding Thermal Management RF/EMI Shielding SOPs +12 more Show less