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ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools +9 more Show less

UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

Physical Design CAD Tools Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI SoC Design Signoff Physical Verification +9 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture ARM V7 Wireless Protocols Power Analysis RTL Design Debugging +12 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python RTL Digital Logic Design Constrained Random Testing Makefile Emulation Wireless Protocols Power Analysis SoC Design +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less

Adobe Creative Suite Microsoft Office Learning Management System LMS Multimedia Content Creation Graphic Design Digital Media Technology Instructional System Design Print Graphics +4 more Show less

UVM System Verilog Python Formal Verification PCIe CXL AXI AMBA CHI Generative AI IP Verification random-stimulus Protocol Bridges +8 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation +9 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation +9 more Show less

Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design Storage Designs Emulation Validation +10 more Show less

ASIC Design SystemVerilog Verilog HDL UVM RTL Design FPGA Static Timing Analysis (STA) Logic Synthesis Lint CDC IP Integration PPA Machine Learning LLM Acceleration NPU TCP/IP Ethernet Altera AMD Xilinx +14 more Show less

IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan +11 more Show less

Silicon Photonics Cadence Virtuoso GDS Python Matlab Labview HFSS S-parameters PIC Design Tapeout Post-Fab Validation Data Analysis AI Tools CPO NPO OCI +11 more Show less

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal +10 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation +9 more Show less