Principal ASIC Design

Fortinet

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Sunnyvale, CA
Salary
$192,000–$235,000 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k
This role $214k
$144k $261k
below market most similar roles pay here above market

This role pays more than 51% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $214k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Fortinet

Fortinet is a US-based cybersecurity company best known for its FortiGate next-generation firewalls. It sells a broad security platform spanning network security, SD-WAN, endpoint protection, cloud security, and SIEM/SOC operations.

Fortinet currently has 102 open roles on FindRole.

Listed pay typically runs $140,000–$183,000 across 77 roles with salary data.

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At a glance

TL;DR · Principal ASIC Design

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The Principal ASIC Design role sits within the R&D team, where the designer will architect and design next-generation FortiASIC technology to accelerate network security systems. The position involves leading the development of AI-powered network processing ASIC architecture, performing IP integration, and delivering chip-level RTL design and verification. Key responsibilities include defining micro-architecture, performing logic synthesis, conducting Static Timing Analysis, and managing FPGA prototyping for debug cycles. The candidate must utilize SystemVerilog, Verilog HDL, and UVM verification methodologies while managing Lint/CDC reviews and PPA optimization. Technical requirements include deep knowledge of computer networking, Ethernet protocols, the TCP/IP stack, and machine learning or LLM acceleration. This role specifically addresses the technical challenge of designing high-performance NPUs and custom domain-specific accelerators for modern networking.

Skills

ASIC Design SystemVerilog Verilog HDL UVM RTL Design FPGA Static Timing Analysis (STA) Logic Synthesis Lint CDC IP Integration PPA Machine Learning LLM Acceleration NPU TCP/IP Ethernet Altera AMD Xilinx

What you'll do

  • Define and refine the micro-architecture for next-generation FortiASICs.
  • Implement designs using SystemVerilog/Verilog HDL and manage IP integration.
  • Conduct Lint/CDC reviews, logic synthesis, and Static Timing Analysis (STA).
  • Review test plans and perform coverage analysis for full-chip simulations.
  • Optimize placement, routing, and timing to achieve optimal Power, Performance, and Area (PPA).
  • Emulate and prototype designs using FPGAs for debug and validation cycles.
  • Participate in system/board-level bring-up and post-silicon debugging.

What we're looking for

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
  • 8+ years of experience in high-performance networking or processor design.
  • Proven track record of taking complex ASIC/FPGA designs from initial concept to mass production.
  • Hands-on expertise in Verilog/SystemVerilog HDL coding, synthesis, and design verification.
  • Strong understanding of SystemVerilog and UVM verification methodologies.
  • Strong background in AI/LLM accelerator or NPU design.
  • Experience with Altera/AMD Xilinx FPGA architectures, Ethernet protocols, or microprocessor architecture (preferred).

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