ASIC Digital Design Tech Lead

Cisco

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Carlsbad, CAAllentown, PA
Salary: $166,300–$238,300 / yr
Employment: Full-time
Posted: 3 days ago
Freshness: Confirmed live yesterday
Closes: Jan 19, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $198k

This role $202k

$144k $256k

below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $168,200–$227,300 — the blue band above. At the midpoint, this role pays about $202k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Digital Design Tech Lead

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The ASIC Digital Design Tech Lead joins the Silicon One team to architect the backbone of next-generation optical interconnects. This role involves owning the full ASIC lifecycle from initial concept to tapeout and post-silicon production. You will lead cross-functional engineering teams to define digital architectures, specify high-speed datapaths, and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. Key responsibilities include RTL design, GDS2 signoff, FPGA prototyping, and lab validation. You will utilize skills in FSMs, CPU subsystems, and complex SoCs while integrating SerDes and DSP IPs. Required technical competencies include experience with SPI, I2C, APB, AXI, Ethernet, and D2D PHY protocols, alongside synthesis, DFT, low-power design, and automation scripting for processing Quality of Results metrics.

Skills

ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting

What you'll do

Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up.
Translate top-level requirements into high-speed datapath and low-speed control plane block specifications.
Simulate and debug complex design issues while signing off on verification coverage.
Support the integration of SerDes and DSP IPs into the silicon architecture.
Perform backend implementation activities including synthesis, timing closure, and DFT.
Develop automation scripts to process Quality of Results (QoR) metrics.
Optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics.

What we're looking for

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation.
Prior experience in managing the complete ASIC/SoC design flow.
Prior experience with key bus and interface protocols including SPI, I2C, APB, AXI, high-speed SerDes, Ethernet, and D2D PHY IP.
Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff (preferred).
Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes (preferred).
Prior experience reviewing verification coverage metrics, debugging verification issues, and integrating SerDes and DSP IP (preferred).
Hands-on experience with synthesis, timing closure, DFT, low-power design, and design automation scripting (preferred).

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