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Agile R&D Index Design Digital Assets Equities OKR CFA PhD +3 more Show less

RF Circuit Theory ADS Cadence Allegro HDL PCB Layout Labview VHF 900 MHz Power Amplifiers VCO PLL Radio Frequency Transmitters Communication Theory Electrical Engineering +9 more Show less

RF Design PCB Layout Schematic Design Cadence Mentor Graphics AWR Microwave Office Keysight ADS CST FEKO HFSS Vector Network Analyzer Spectrum Analyzer Signal Generator Noise Figure Meter Oscilloscope DMM Antenna Engineering RF Architecture CCA Design +14 more Show less

AI Design Systems Figma Jira GitHub Design Tokens User-Centered Design Design Ops Product Operations Design-to-Engineering Workflows Research Operations Governance Frameworks Program Management +8 more Show less

SoC Architecture SystemVerilog Verilog VHDL AMBA Synthesis Formal Verification CDC DFT Timing Closure Git JIRA DRAM SERDES UART Design Validation +11 more Show less

SoC Design Microarchitecture Logic Design Lint CDC Synthesis ECO Formal Verification STA Physical Design AMBA AXI AHB APB Asynchronous Interfaces +10 more Show less

Acoustics FEA Comsol Ansys Python Matlab C++ C NX UG CAD JMP Excel HW/SW Automation Vibro-acoustic Simulation Transducer Design +11 more Show less

Python SQL Lua Blueprint C# Unity Frostbite Git Perforce Jenkins GitLab CI/CD Miro Figma Telemetry Data Pipelines Quantitative Modeling AI Agents LLM +14 more Show less

ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools +9 more Show less

UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

Physical Design CAD Tools Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI SoC Design Signoff Physical Verification +9 more Show less

Verilog SystemVerilog Python TCL Perl VHDL Spice Power Analysis Formal Verification DRC LVS RC Extraction Machine Learning Data Analysis DFT Library Characterization EDA Tools +12 more Show less

Verilog SystemVerilog Python TCL Perl VHDL Spice Power Analysis Formal Verification DRC LVS RC Extraction Machine Learning Data Analysis DFT Library Characterization EDA Tools +12 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture ARM V7 Wireless Protocols Power Analysis RTL Design Debugging +12 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python RTL Digital Logic Design Constrained Random Testing Makefile Emulation Wireless Protocols Power Analysis SoC Design +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less