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DFT JTAG SCAN BIST RTL ASIC FinFET Synopsys Design Compiler Tetramax Spyglass VCS ATE Python SQL JMP Statistical Process Control ISO 9001 Root Cause Analysis +14 more Show less

DFT CAD Python Tcl Perl Shell Scripting LSF Synopsys TestMAX Synopsys VCS Siemen's Tessent AI Pandas STIL RTL ATPG +10 more Show less

SystemVerilog UVM ASIC Verification Python Perl Hardware Emulation FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR RTL Silicon Bring-up Post-Silicon Validation +13 more Show less

DFT Scan BIST JTAG ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Static Timing Analysis Post-silicon Validation ATE P1687 RTL +12 more Show less

ASIC RTL CDC RDC SDC VCS SystemVerilog Assertions SVA Synthesis Gate Netlists +5 more Show less

System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation +12 more Show less

Mixed-Signal Design Silicon Photonics Cadence Virtuoso Spectre Caliber SystemVerilog Verilog-AMS Python C SerDes PAM4 TIA ADC DAC DFT SI/PI Ethernet UCIE Verilog-A +14 more Show less

Python C/C++ MATLAB IBIS-AMI ADS HSPICE Cadence Linux Perl TCL SerDes PAM4 DSP Ethernet Signal Integrity ASIC SoC +12 more Show less

System Verilog UVM Verilog Python Perl TCL Formal Verification ASIC Design Verification Ethernet UCIE SPI I2C Veloce HAPS SerDes PAM4 +11 more Show less