ASIC Technical Leader, CAD

Cisco

Confirmed live yesterday High trust

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $186,900–$267,700 / yr
Posted: 17 days ago
Freshness: Confirmed live yesterday
Closes: Oct 2, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $227k

$146k most similar roles pay here $281k

This role pays more than 72% of similar roles. Most pay $177,250–$232,000 — the shaded band above. At the midpoint, this role pays about $227k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Technical Leader, CAD

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As an ASIC Technical Leader- CAD within the Common Hardware Group, you will own and drive end-to-end DFT flow architecture while building and maintaining scalable CAD infrastructure across the entire design cycle from RTL and insertion to ATPG, simulation, and reporting. You will spearhead the development of robust, LSF-based regression frameworks and leverage AI-driven automation for log analysis, failure triage, and intelligent debug processes. Collaborating cross-functionally with RTL, Physical Design, and Validation teams, you will ensure seamless integration and establish standardized, high-reusability flows. The role requires expertise in Tcl, Python, Perl, and shell scripting, alongside experience with EDA toolchains like Synopsys TestMAX, Synopsys VCS, and Siemens Tessent. You will solve complex technical challenges involving SoC integration and automated flow development for advanced networking hardware products including switching, routing, and wireless platforms.

Skills

DFT CAD Python Tcl Perl Shell Scripting LSF Synopsys TestMAX Synopsys VCS Siemen's Tessent AI Pandas STIL RTL ATPG

What you'll do

Own and drive end-to-end DFT flow architecture for complex ASICs.
Build and maintain scalable CAD infrastructure across the entire design cycle from RTL to ATPG.
Develop robust, LSF-based regression frameworks for automated testing.
Implement AI-driven automation to enhance log analysis, failure triage, and debug processes.
Establish standardized, high-reusability flows that enforce best practices for cross-functional teams.
Manage the integration and signoff of DFT tools with RTL, Physical Design, and Validation teams.

What we're looking for

8+ years of experience in CAD or test automation for semiconductor designs.
Experience applying AI/ML techniques to EDA workflows like log analysis and anomaly detection.
Experience with EDA DFT toolchains including Synopsys TestMAX, Synopsys VCS, and Siemens Tessent.
Proficiency in Tcl, Python, Perl, and shell scripting.
Experience building automated flows and regression systems in compute farm environments using LSF or similar tools.
Experience with SoC integration and cross-functional workflows.
Familiarity with data analytics tools including Python/pandas and visualization dashboards.
Exposure to ATE/tester formats such as STIL and experience with silicon bring-up/debug.

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