ASIC Technical Leader, CAD

Cisco

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today
Closes
Nov 13, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $227k
$141k $281k
below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $177,250–$227,300 — the blue band above. At the midpoint, this role pays about $227k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Technical Leader, CAD

Role Posting Log in to save

As an ASIC Technical Leader- CAD within the Common Hardware Group, you will own and drive the end-to-end DFT flow architecture for complex networking silicon. You will build and maintain scalable CAD infrastructure spanning the entire design cycle, from RTL and insertion to ATPG, simulation, and reporting. Your daily responsibilities include spearheading the development of robust, LSF-based regression frameworks and leveraging AI-driven automation for log analysis, failure triage, and intelligent debug processes. You will collaborate cross-functionally with RTL, Physical Design, and Validation teams to ensure seamless integration and signoff. Required technical skills include experience with Synopsys TestMAX, Synopsys VCS, and Siemens Tessent, alongside proficiency in Tcl, Python, Perl, and shell scripting. You will solve complex hardware problems by establishing standardized, high-reusability flows for unified routing and switching portfolios.

Skills

DFT CAD Python Tcl Perl Shell Scripting LSF Synopsys TestMAX Synopsys VCS Siemen's Tessent AI ML Pandas STIL ATPG RTL SoC Integration

What you'll do

  • Own and drive the end-to-end DFT flow architecture for complex ASICs.
  • Build and maintain scalable CAD infrastructure spanning the entire design cycle from RTL to ATPG.
  • Develop robust, LSF-based regression frameworks for automated testing.
  • Leverage AI-driven automation to enhance log analysis, failure triage, and debug processes.
  • Ensure seamless integration and signoff by collaborating with RTL, Physical Design, and Validation teams.
  • Establish standardized, high-reusability flows that enforce industry best practices.

What we're looking for

  • 8+ years of experience in CAD or test automation for semiconductor designs.
  • Experience applying AI/ML techniques to EDA workflows for log analysis, anomaly detection, and predictive insights.
  • Prior experience with EDA DFT toolchains such as Synopsys TestMAX, Synopsys VCS, and Siemens Tessent.
  • Experience in Tcl, Python, Perl, and shell scripting.
  • Experience building automated flows and regression systems in compute farm environments like LSF.
  • Prior experience with SoC integration and cross-functional workflows.
  • Familiarity with data analytics tools including Python/pandas, dashboards, and visualization tools (preferred).
  • Experience with large-scale regression systems, distributed job management, ATE/tester formats, and silicon bring-up/debug (preferred).

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