ASIC Digital Design Technical Leader

What you'll do

• Architect the backbone of next-generation optical interconnects from initial concept to post-silicon production.
• Own the full ASIC lifecycle including design, tapeout, and cross-functional leadership across digital, analog, and firmware teams.
• Define digital architectures and integrate high-speed IPs such as SerDes, D2D IP, and 400G silicon photonics.
• Develop top and block-level specifications for high-speed datapath and low-speed control planes.
• Manage power and timing budgeting while resolving hardware versus firmware trade-offs.
• Review verification coverage metrics and independently debug complex issues in the verification flow.
• Oversee backend implementation activities including synthesis, timing closure, DFT, and design automation scripting.
• Drive technical strategy to optimize performance for high-performance computing infrastructure.

What we're looking for

• Bachelor's degree plus 12 years experience, Master's plus 8 years, or PhD plus 5 years of related experience.
• Experience in digital design with FSMs, CPU sub-systems, complex SoCs, and FPGA validation.
• Experience managing the complete ASIC/SoC design flow.
• Experience with bus and interface protocols such as SPI, I2C, APB, AXI, SerDes, Ethernet, and D2D PHY IP.
• Experience leading architecture and design of digital blocks from RTL to GDS2 signoff through post-silicon validation (preferred).
• Experience developing top and block-level specifications for high-speed datapath and low-speed control planes (preferred).
• Experience with verification coverage, debugging, firmware-based verification, and integrating SerDes and DSP IP (preferred).
• Experience with backend implementation including synthesis, timing closure, DFT, and design automation scripting (preferred).