ASIC Technical Leader, Product Quality & Productization

Cisco

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$214,100–$309,800 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Sep 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $262k
$146k most similar roles pay here $327k

This role pays more than 92% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $262k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Technical Leader, Product Quality & Productization

ASIC Technical Leader - Product Quality & Productization provides high-level technical leadership for the Silicon One organization within the Hardware Engineering team. This role bridges the gap between advanced DFT architecture, silicon quality, and high-volume manufacturing to ensure programmable silicon maintains standards for reliability, yield, and field performance. The individual will direct the development of robust DFT architectures including JTAG, SCAN, and BIST, while orchestrating the transition of complex SoC products from RTL design through New Product Introduction to mass production. Key responsibilities include leading root cause analysis, overseeing product qualification like environmental stress screening, and monitoring manufacturing data for yield optimization. The role requires expertise in advanced FinFET processes, the Synopsys suite including Design Compiler, Tetramax, Spyglass, and VCS, as well as ATE 93K testers, with additional proficiency in Python, SQL, and JMP.

What you'll do

  • Direct the development and execution of robust DFT architectures including JTAG, SCAN, and BIST.
  • Integrate Design-for-Manufacturability (DFM) and DFT principles into the early stages of the development cycle.
  • Manage the transition of complex SoC products from initial design through NPI to mass production.
  • Lead high-level Root Cause Analysis (RCA) using advanced diagnostics to drive corrective actions.
  • Supervise product qualification processes including environmental stress screening, electrical characterization, and life testing.
  • Implement yield analysis, power binning, and fuse array repairs to minimize defect parts per million.
  • Monitor manufacturing data to identify trends and optimize process windows for continuous yield improvement.
  • Maintain comprehensive technical documentation for all quality plans in accordance with global standards.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 20+ years of experience in Silicon DFT, Test, Quality, and Program Management.
  • Minimum of 5 years of experience specifically within high-reliability hardware environments.
  • Deep knowledge of the full ASIC development lifecycle and advanced FinFET processes (6nm/7nm).
  • Mastery of the Synopsys suite including Design Compiler, Tetramax, Spyglass, and VCS.
  • Proficiency with ATE (93K testers).
  • Validated expertise in Statistical Process Control (SPC) and diagnostic tools like JMP, Python, or SQL (preferred).
  • Proven success leading multidisciplinary teams and translating complex data into executive insights (preferred).

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