ASIC Technical Leader, Product Quality & Productization

Cisco

Confirmed live yesterday High trust
Closes in 4 days Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Employment
Full-time
Posted
28 days ago
Freshness
Confirmed live yesterday
Closes
Oct 31, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

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Similar $202k
$155k $255k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $177,250–$227,500.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Technical Leader, Product Quality & Productization

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The ASIC Technical Leader - Product Quality & Productization provides high-level technical leadership for the Silicon One organization within the Hardware Engineering Team. This role bridges the gap between advanced DFT architecture, silicon quality, and high-volume manufacturing for programmable silicon architecture. Key responsibilities include directing DFT architectures like JTAG, SCAN, and BIST, orchestrating transitions from RTL design through New Product Introduction to mass production, and leading Root Cause Analysis initiatives. The position requires managing yield optimization, power binning, and environmental stress screening while ensuring adherence to ISO 9001 standards. Candidates must possess deep knowledge of advanced FinFET processes, the Synopsys suite including Design Compiler, Tetramax, Spyglass, and VCS, and ATE 93K testers. Proficiency in Statistical Process Control, Python, and SQL is also required.

Skills

DFT ASIC RTL JTAG SCAN BIST DFM FinFET Synopsys Design Compiler Tetramax Spyglass VCS ATE JMP Python SQL SPC ISO 9001

What you'll do

  • Direct the development and execution of robust DFT architectures including JTAG, SCAN, and BIST.
  • Integrate Design-for-Manufacturability and DFT principles into the early stages of the development cycle.
  • Orchestrate the transition of complex SoC products from development through NPI to mass production.
  • Manage program risks and provide executive-level status reporting on manufacturing health and yield.
  • Lead high-level Root Cause Analysis initiatives using advanced diagnostics to drive corrective actions.
  • Supervise product qualification including Environmental Stress Screening, electrical characterization, and accelerated life testing.
  • Implement advanced yield analysis, power binning, and fuse array repairs to minimize DPPM.
  • Monitor high-volume manufacturing data to identify trends and optimize process windows.

What we're looking for

  • 20+ years of experience in Silicon DFT, Test, Quality, and Program Management.
  • Minimum of 5 years of experience specifically within high-reliability hardware environments.
  • Deep knowledge of the full ASIC development lifecycle, specifically within the Silicon One pipeline and advanced FinFET processes (6nm/7nm).
  • Mastery of Synopsys suite (Design Compiler, Tetramax, Spyglass, VCS) and ATE (93K testers).
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • Validated expertise in Statistical Process Control (SPC) and diagnostic tools such as JMP, Python, and SQL (preferred).
  • Proven success in leading multidisciplinary teams and translating complex data into actionable executive insights (preferred).

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