This role pays more than
75%
of similar roles. Most pay
$177,250–$232,225
— the shaded band above.
At the midpoint, this role pays about
$234k
versus about
$205k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
240 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,000
across 188 roles with salary data.
As an ASIC Engineering Technical Leader, you will join the Silicon One team to drive the definition, architecture, design, and productization of high-performance mixed-signal ASICs, subsystems, or specialized DFT domains. You will own the architecture for blocks and frameworks while partnering with experts to solve complex cross-functional challenges. Your daily responsibilities include developing reusable designs, creating automated flows and scripts, and leading technical engagements with tool vendors and IP suppliers. You will implement robust verification strategies for high-speed digital and custom analog blocks using AI and agent-based script creation to improve efficiency. The role requires expertise in DFT architecture, at-speed scan, MBIST, BISR, boundary-scan, and parametric testing techniques. This position focuses on the development of optical engines, specifically EIC and PIC technologies targeted for high-growth AI and datacenter applications.
Drive the definition, architecture, design, and productization of high-performance mixed-signal ASICs and subsystems.
Own the architecture and definition for specific blocks, subsystems, or DFT frameworks.
Develop and implement robust verification strategies for both high-speed digital and custom analog blocks.
Create reusable designs and automated flows or scripts to improve team efficiency.
Lead technical engagements with tool vendors and IP suppliers.
Utilize AI and agent-based tools to automate script creation, verification, and debug flows.
Champion methodology developments that can be scaled across multiple product lines.
What we're looking for
Bachelor's degree plus 12 years of related experience, or Master's plus 8 years, or PhD plus 5 years.
Experience in the definition, architecture, design, and productization of high-performance mixed-signal ASICs or subsystems.
Ability to lead project-level design and develop scalable methodology for multiple product lines.
Expertise in creating robust verification strategies for both high-speed digital and custom analog blocks.
Proficiency in developing reusable designs and automated flows/scripts using AI and agent-based tools.
Experience owning DFT architecture development for an SoC from concept through mass production (preferred).
Experience implementing at-speed scan, MBIST, BISR, boundary-scan, and custom techniques for parametric testing of analog and mixed-signal blocks (preferred).