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C/C++ UVM System C DPI-C Matlab

UVM SystemVerilog C Matlab Python DPI-C SystemC Formal verification Verilog VCS DVflow CI/CD +7 more Show less

RTL Verilog SystemVerilog VHDL SoC IP integration Ethernet SERDES LPDDR5/6X Arm CPU 3rd party IP blocks low power design DFT synthesis STA physical design deep sub-micron nodes communication systems wireless communications serial protocols SPI I2C I3C UART +19 more Show less

UVM Matlab SystemC DPI-C Verilog VHDL RTL Python CI/CD AWS Linux Git SVN JIRA Confluence +10 more Show less

UVM SystemVerilog C SystemC DPI-C Matlab +1 more Show less

MATLAB UVM SystemC DPI-C RTL DSP Verilog VHDL Linux Python Git CI/CD ASIC FPGA Simulation Verification Power Optimization Timing Optimization +13 more Show less

RTL UVM SystemC DPI-C DSP MATLAB Verilog VHDL ASIC CMOS Linux Git CI/CD Python PostgreSQL +10 more Show less

SystemC UVM DPI-C RTL DSP Matlab Verilog VHDL Linux Python Git CI/CD FPGA ASIC PowerPC Xilinx Cadence Synopsys Tapeout +14 more Show less

C/C++ UVM SystemC DPI-C Matlab

C/C++ UVM SystemC DPI-C Matlab

SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification +7 more Show less

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

SystemVerilog UVM SystemVerilog-UVM Perl Python C++ C VHDL Formal Verification Assertion Based Formal Verification AMBA Bus Protocol AXI AHB APB +9 more Show less

C++ Python Tcl Perl Shell VCS DC PT PrimeTime ICC2 Calibre OpenAccess Verilog SystemVerilog Linux Git CI/CD Docker +13 more Show less

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3 +9 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl UPF CPF SDC CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less

Cadence_Virtuoso Python Matlab ASIC SerDes DDR PLL DAC ADC Sensors Design_for_Yield Signals_and_Systems Sampled_Domain_Signal_Processing +8 more Show less

Cadence_Virtuoso Matlab Python PLL RXAFE CTLE CDR DAC ADC Signals_and_Systems Sampled_Domain_Signal_Processing Design_for_Yield High_Speed_Serial_Links +8 more Show less

VCS Fusion Compiler PrimeTime Power Compiler (PTPX) DFT Compiler Spyglass Python Perl +3 more Show less